^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tegra20_das.h - Definitions for Tegra20 DAS driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Stephen Warren <swarren@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2010,2012 - NVIDIA, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __TEGRA20_DAS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __TEGRA20_DAS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* Register TEGRA20_DAS_DAP_CTRL_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TEGRA20_DAS_DAP_CTRL_SEL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TEGRA20_DAS_DAP_CTRL_SEL_COUNT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TEGRA20_DAS_DAP_CTRL_SEL_STRIDE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Values for field TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA20_DAS_DAP_SEL_DAC1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA20_DAS_DAP_SEL_DAC2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA20_DAS_DAP_SEL_DAC3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA20_DAS_DAP_SEL_DAP1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA20_DAS_DAP_SEL_DAP2 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA20_DAS_DAP_SEL_DAP3 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA20_DAS_DAP_SEL_DAP4 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA20_DAS_DAP_SEL_DAP5 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Register TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Values for:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEGRA20_DAS_DAC_SEL_DAP1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TEGRA20_DAS_DAC_SEL_DAP2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TEGRA20_DAS_DAC_SEL_DAP3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TEGRA20_DAS_DAC_SEL_DAP4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TEGRA20_DAS_DAC_SEL_DAP5 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Names/IDs of the DACs/DAPs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TEGRA20_DAS_DAP_ID_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TEGRA20_DAS_DAP_ID_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TEGRA20_DAS_DAP_ID_3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TEGRA20_DAS_DAP_ID_4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TEGRA20_DAS_DAP_ID_5 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TEGRA20_DAS_DAC_ID_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TEGRA20_DAS_DAC_ID_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TEGRA20_DAS_DAC_ID_3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct tegra20_das {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Terminology:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * DAS: Digital audio switch (HW module controlled by this driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * DAP: Digital audio port (port/pins on Tegra device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * DAC: Digital audio controller (e.g. I2S or AC97 controller elsewhere)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * The Tegra DAS is a mux/cross-bar which can connect each DAP to a specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * DAC, or another DAP. When DAPs are connected, one must be the master and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * one the slave. Each DAC allows selection of a specific DAP for input, to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * cater for the case where N DAPs are connected to 1 DAC for broadcast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * This driver is dumb; no attempt is made to ensure that a valid routing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * configuration is programmed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Connect a DAP to a DAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * dac_sel: DAC to connect to: TEGRA20_DAS_DAP_SEL_DAC*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) extern int tegra20_das_connect_dap_to_dac(int dap_id, int dac_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Connect a DAP to another DAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * other_dap_sel: DAP to connect to: TEGRA20_DAS_DAP_SEL_DAP*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * master: Is this DAP the master (1) or slave (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * sdata1rx: Is this DAP's SDATA1 pin RX (1) or TX (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * sdata2rx: Is this DAP's SDATA2 pin RX (1) or TX (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) extern int tegra20_das_connect_dap_to_dap(int dap_id, int other_dap_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int master, int sdata1rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int sdata2rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Connect a DAC's input to a DAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * (DAC outputs are selected by the DAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * dac_id: DAC ID to connect: TEGRA20_DAS_DAC_ID_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * dap_sel: DAP to receive input from: TEGRA20_DAS_DAC_SEL_DAP*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) extern int tegra20_das_connect_dac_to_dap(int dac_id, int dap_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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