Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * tegra20_das.c - Tegra20 DAS driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Stephen Warren <swarren@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2010 - NVIDIA, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "tegra20_das.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define DRV_NAME "tegra20-das"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static struct tegra20_das *das;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static inline void tegra20_das_write(u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	regmap_write(das->regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static inline u32 tegra20_das_read(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	regmap_read(das->regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) int tegra20_das_connect_dap_to_dac(int dap, int dac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	if (!das)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	addr = TEGRA20_DAS_DAP_CTRL_SEL +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		(dap * TEGRA20_DAS_DAP_CTRL_SEL_STRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	reg = dac << TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	tegra20_das_write(addr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) EXPORT_SYMBOL_GPL(tegra20_das_connect_dap_to_dac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) int tegra20_das_connect_dap_to_dap(int dap, int otherdap, int master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 				   int sdata1rx, int sdata2rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	if (!das)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	addr = TEGRA20_DAS_DAP_CTRL_SEL +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		(dap * TEGRA20_DAS_DAP_CTRL_SEL_STRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	reg = otherdap << TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		!!sdata2rx << TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		!!sdata1rx << TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		!!master << TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	tegra20_das_write(addr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) EXPORT_SYMBOL_GPL(tegra20_das_connect_dap_to_dap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) int tegra20_das_connect_dac_to_dap(int dac, int dap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	if (!das)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	addr = TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		(dac * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	reg = dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	tegra20_das_write(addr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) EXPORT_SYMBOL_GPL(tegra20_das_connect_dac_to_dap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define LAST_REG(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	(TEGRA20_DAS_##name + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 (TEGRA20_DAS_##name##_STRIDE * (TEGRA20_DAS_##name##_COUNT - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static bool tegra20_das_wr_rd_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (reg <= LAST_REG(DAP_CTRL_SEL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	if ((reg >= TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	    (reg <= LAST_REG(DAC_INPUT_DATA_CLK_SEL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const struct regmap_config tegra20_das_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.max_register = LAST_REG(DAC_INPUT_DATA_CLK_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.writeable_reg = tegra20_das_wr_rd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.readable_reg = tegra20_das_wr_rd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int tegra20_das_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (das)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	das = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_das), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (!das) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	das->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (IS_ERR(regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		ret = PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	das->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 					    &tegra20_das_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (IS_ERR(das->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		dev_err(&pdev->dev, "regmap init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		ret = PTR_ERR(das->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	ret = tegra20_das_connect_dap_to_dac(TEGRA20_DAS_DAP_ID_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 					     TEGRA20_DAS_DAP_SEL_DAC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		dev_err(&pdev->dev, "Can't set up DAS DAP connection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	ret = tegra20_das_connect_dac_to_dap(TEGRA20_DAS_DAC_ID_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 					     TEGRA20_DAS_DAC_SEL_DAP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		dev_err(&pdev->dev, "Can't set up DAS DAC connection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	ret = tegra20_das_connect_dap_to_dac(TEGRA20_DAS_DAP_ID_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 					     TEGRA20_DAS_DAP_SEL_DAC3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		dev_err(&pdev->dev, "Can't set up DAS DAP connection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	ret = tegra20_das_connect_dac_to_dap(TEGRA20_DAS_DAC_ID_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 					     TEGRA20_DAS_DAC_SEL_DAP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		dev_err(&pdev->dev, "Can't set up DAS DAC connection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	platform_set_drvdata(pdev, das);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	das = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int tegra20_das_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (!das)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	das = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct of_device_id tegra20_das_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	{ .compatible = "nvidia,tegra20-das", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static struct platform_driver tegra20_das_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.probe = tegra20_das_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.remove = tegra20_das_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		.name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.of_match_table = tegra20_das_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) module_platform_driver(tegra20_das_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MODULE_DESCRIPTION("Tegra20 DAS driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MODULE_ALIAS("platform:" DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MODULE_DEVICE_TABLE(of, tegra20_das_of_match);