^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tegra20_ac97.h - Definitions for the Tegra20 AC97 controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2012 Lucas Stach <dev@lynxeye.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Partly based on code copyright/by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2011,2012 Toradex Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __TEGRA20_AC97_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __TEGRA20_AC97_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "tegra_pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TEGRA20_AC97_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TEGRA20_AC97_CMD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA20_AC97_STATUS1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEGRA20_AC97_FIFO1_SCR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA20_AC97_FIFO_TX1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA20_AC97_FIFO_RX1 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* TEGRA20_AC97_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA20_AC97_CTRL_STM2_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA20_AC97_CTRL_DOUBLE_SAMPLING_EN (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA20_AC97_CTRL_IO_CNTRL_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA20_AC97_CTRL_HSET_DAC_EN (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA20_AC97_CTRL_LINE2_DAC_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA20_AC97_CTRL_PCM_LFE_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA20_AC97_CTRL_PCM_SUR_EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA20_AC97_CTRL_PCM_CEN_DAC_EN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA20_AC97_CTRL_LINE1_DAC_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA20_AC97_CTRL_PCM_DAC_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA20_AC97_CTRL_COLD_RESET (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA20_AC97_CTRL_WARM_RESET (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA20_AC97_CTRL_STM_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* TEGRA20_AC97_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEGRA20_AC97_CMD_CMD_ADDR_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA20_AC97_CMD_CMD_ADDR_MASK (0xff << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA20_AC97_CMD_CMD_DATA_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TEGRA20_AC97_CMD_CMD_DATA_MASK (0xffff << TEGRA20_AC97_CMD_CMD_DATA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEGRA20_AC97_CMD_CMD_ID_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TEGRA20_AC97_CMD_CMD_ID_MASK (0x3 << TEGRA20_AC97_CMD_CMD_ID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEGRA20_AC97_CMD_BUSY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* TEGRA20_AC97_STATUS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TEGRA20_AC97_STATUS1_STA_ADDR1_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEGRA20_AC97_STATUS1_STA_ADDR1_MASK (0xff << TEGRA20_AC97_STATUS1_STA_ADDR1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TEGRA20_AC97_STATUS1_STA_DATA1_MASK (0xffff << TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TEGRA20_AC97_STATUS1_STA_VALID1 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TEGRA20_AC97_STATUS1_STANDBY1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TEGRA20_AC97_STATUS1_CODEC1_RDY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* TEGRA20_AC97_FIFO1_SCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_MASK (0x1f << TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_MASK (0x1f << TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TEGRA20_AC97_FIFO_SCR_REC_OVERRUN_INT_STA (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TEGRA20_AC97_FIFO_SCR_PB_UNDERRUN_INT_STA (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TEGRA20_AC97_FIFO_SCR_REC_FORCE_MT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TEGRA20_AC97_FIFO_SCR_PB_FORCE_MT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TEGRA20_AC97_FIFO_SCR_REC_FULL_EN (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TEGRA20_AC97_FIFO_SCR_REC_3QRT_FULL_EN (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TEGRA20_AC97_FIFO_SCR_REC_QRT_FULL_EN (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TEGRA20_AC97_FIFO_SCR_REC_EMPTY_EN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TEGRA20_AC97_FIFO_SCR_PB_NOT_FULL_EN (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TEGRA20_AC97_FIFO_SCR_PB_3QRT_MT_EN (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TEGRA20_AC97_FIFO_SCR_PB_EMPTY_MT_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct tegra20_ac97 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct clk *clk_ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct snd_dmaengine_dai_dma_data capture_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct snd_dmaengine_dai_dma_data playback_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int sync_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #endif /* __TEGRA20_AC97_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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