Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // tegra186_dspk.c - Tegra186 DSPK driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "tegra186_dspk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "tegra_cif.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static const struct reg_default tegra186_dspk_reg_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	{ TEGRA186_DSPK_RX_INT_MASK, 0x00000007 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	{ TEGRA186_DSPK_RX_CIF_CTRL, 0x00007700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	{ TEGRA186_DSPK_CG,	     0x00000001 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	{ TEGRA186_DSPK_CORE_CTRL,   0x00000310 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	{ TEGRA186_DSPK_CODEC_CTRL,  0x03000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static int tegra186_dspk_get_fifo_th(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 				     struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	ucontrol->value.integer.value[0] = dspk->rx_fifo_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static int tegra186_dspk_put_fifo_th(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 				     struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	int value = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	if (value == dspk->rx_fifo_th)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	dspk->rx_fifo_th = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static int tegra186_dspk_get_osr_val(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 				     struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	ucontrol->value.enumerated.item[0] = dspk->osr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static int tegra186_dspk_put_osr_val(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 				     struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	unsigned int value = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	if (value == dspk->osr_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	dspk->osr_val = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static int tegra186_dspk_get_pol_sel(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 				     struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	ucontrol->value.enumerated.item[0] = dspk->lrsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static int tegra186_dspk_put_pol_sel(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 				     struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	unsigned int value = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (value == dspk->lrsel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	dspk->lrsel = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int tegra186_dspk_get_ch_sel(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 				    struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ucontrol->value.enumerated.item[0] = dspk->ch_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int tegra186_dspk_put_ch_sel(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 				    struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	unsigned int value = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (value == dspk->ch_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	dspk->ch_sel = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int tegra186_dspk_get_mono_to_stereo(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 					    struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	ucontrol->value.enumerated.item[0] = dspk->mono_to_stereo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int tegra186_dspk_put_mono_to_stereo(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 					    struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	unsigned int value = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (value == dspk->mono_to_stereo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	dspk->mono_to_stereo = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int tegra186_dspk_get_stereo_to_mono(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 					    struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	ucontrol->value.enumerated.item[0] = dspk->stereo_to_mono;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int tegra186_dspk_put_stereo_to_mono(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 					    struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	unsigned int value = ucontrol->value.enumerated.item[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (value == dspk->stereo_to_mono)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	dspk->stereo_to_mono = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int __maybe_unused tegra186_dspk_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct tegra186_dspk *dspk = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	regcache_cache_only(dspk->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	regcache_mark_dirty(dspk->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	clk_disable_unprepare(dspk->clk_dspk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int __maybe_unused tegra186_dspk_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct tegra186_dspk *dspk = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	err = clk_prepare_enable(dspk->clk_dspk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		dev_err(dev, "failed to enable DSPK clock, err: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	regcache_cache_only(dspk->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	regcache_sync(dspk->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int tegra186_dspk_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				   struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 				   struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct tegra186_dspk *dspk = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	unsigned int channels, srate, dspk_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct device *dev = dai->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	struct tegra_cif_conf cif_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	unsigned int max_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	cif_conf.audio_ch = channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/* Client channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	switch (dspk->ch_sel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	case DSPK_CH_SELECT_LEFT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	case DSPK_CH_SELECT_RIGHT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		cif_conf.client_ch = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	case DSPK_CH_SELECT_STEREO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		cif_conf.client_ch = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		dev_err(dev, "Invalid DSPK client channels\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	cif_conf.client_bits = TEGRA_ACIF_BITS_24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		cif_conf.audio_bits = TEGRA_ACIF_BITS_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		cif_conf.audio_bits = TEGRA_ACIF_BITS_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		dev_err(dev, "unsupported format!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	srate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	/* RX FIFO threshold in terms of frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	max_th = (TEGRA186_DSPK_RX_FIFO_DEPTH / cif_conf.audio_ch) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (dspk->rx_fifo_th > max_th)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		dspk->rx_fifo_th = max_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	cif_conf.threshold = dspk->rx_fifo_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	cif_conf.mono_conv = dspk->mono_to_stereo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	cif_conf.stereo_conv = dspk->stereo_to_mono;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	tegra_set_cif(dspk->regmap, TEGRA186_DSPK_RX_CIF_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		      &cif_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	 * DSPK clock and PDM codec clock should be synchronous with 4:1 ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	 * this is because it takes 4 clock cycles to send out one sample to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	 * codec by sigma delta modulator. Finally the clock rate is a multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	 * of 'Over Sampling Ratio', 'Sample Rate' and 'Interface Clock Ratio'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	dspk_clk = (DSPK_OSR_FACTOR << dspk->osr_val) * srate * DSPK_CLK_RATIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	err = clk_set_rate(dspk->clk_dspk, dspk_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		dev_err(dev, "can't set DSPK clock rate %u, err: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			dspk_clk, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	regmap_update_bits(dspk->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			   /* Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			   TEGRA186_DSPK_CORE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			   /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			   TEGRA186_DSPK_OSR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			   TEGRA186_DSPK_CHANNEL_SELECT_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			   TEGRA186_DSPK_CTRL_LRSEL_POLARITY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			   /* Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			   (dspk->osr_val << DSPK_OSR_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			   ((dspk->ch_sel + 1) << CH_SEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			   (dspk->lrsel << LRSEL_POL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const struct snd_soc_dai_ops tegra186_dspk_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.hw_params	= tegra186_dspk_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static struct snd_soc_dai_driver tegra186_dspk_dais[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	    .name = "DSPK-CIF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	    .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		.stream_name = "CIF-Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		.channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		.channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		.rates = SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		.formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			   SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	    },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	    .name = "DSPK-DAP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	    .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		.stream_name = "DAP-Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		.channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		.channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		.rates = SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		.formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			   SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	    },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	    .ops = &tegra186_dspk_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	    .symmetric_rates = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct snd_soc_dapm_widget tegra186_dspk_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	SND_SOC_DAPM_AIF_IN("RX", NULL, 0, TEGRA186_DSPK_ENABLE, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	SND_SOC_DAPM_SPK("SPK", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const struct snd_soc_dapm_route tegra186_dspk_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	{ "XBAR-Playback",	NULL,	"XBAR-TX" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	{ "CIF-Playback",	NULL,	"XBAR-Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	{ "RX",			NULL,	"CIF-Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	{ "DAP-Playback",	NULL,	"RX" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	{ "SPK",		NULL,	"DAP-Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const char * const tegra186_dspk_ch_sel_text[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	"Left", "Right", "Stereo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const struct soc_enum tegra186_dspk_ch_sel_enum =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra186_dspk_ch_sel_text),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			tegra186_dspk_ch_sel_text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const char * const tegra186_dspk_osr_text[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	"OSR_32", "OSR_64", "OSR_128", "OSR_256",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const struct soc_enum tegra186_dspk_osr_enum =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra186_dspk_osr_text),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			tegra186_dspk_osr_text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const char * const tegra186_dspk_lrsel_text[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	"Left", "Right",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const char * const tegra186_dspk_mono_conv_text[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	"Zero", "Copy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const struct soc_enum tegra186_dspk_mono_conv_enum =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 			ARRAY_SIZE(tegra186_dspk_mono_conv_text),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			tegra186_dspk_mono_conv_text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const char * const tegra186_dspk_stereo_conv_text[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	"CH0", "CH1", "AVG",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const struct soc_enum tegra186_dspk_stereo_conv_enum =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			ARRAY_SIZE(tegra186_dspk_stereo_conv_text),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 			tegra186_dspk_stereo_conv_text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const struct soc_enum tegra186_dspk_lrsel_enum =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra186_dspk_lrsel_text),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			tegra186_dspk_lrsel_text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const struct snd_kcontrol_new tegrat186_dspk_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	SOC_SINGLE_EXT("FIFO Threshold", SND_SOC_NOPM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		       TEGRA186_DSPK_RX_FIFO_DEPTH - 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		       tegra186_dspk_get_fifo_th, tegra186_dspk_put_fifo_th),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	SOC_ENUM_EXT("OSR Value", tegra186_dspk_osr_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		     tegra186_dspk_get_osr_val, tegra186_dspk_put_osr_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	SOC_ENUM_EXT("LR Polarity Select", tegra186_dspk_lrsel_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		     tegra186_dspk_get_pol_sel, tegra186_dspk_put_pol_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	SOC_ENUM_EXT("Channel Select", tegra186_dspk_ch_sel_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		     tegra186_dspk_get_ch_sel, tegra186_dspk_put_ch_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	SOC_ENUM_EXT("Mono To Stereo", tegra186_dspk_mono_conv_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		     tegra186_dspk_get_mono_to_stereo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		     tegra186_dspk_put_mono_to_stereo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	SOC_ENUM_EXT("Stereo To Mono", tegra186_dspk_stereo_conv_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		     tegra186_dspk_get_stereo_to_mono,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		     tegra186_dspk_put_stereo_to_mono),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const struct snd_soc_component_driver tegra186_dspk_cmpnt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	.dapm_widgets = tegra186_dspk_widgets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	.num_dapm_widgets = ARRAY_SIZE(tegra186_dspk_widgets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.dapm_routes = tegra186_dspk_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	.num_dapm_routes = ARRAY_SIZE(tegra186_dspk_routes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	.controls = tegrat186_dspk_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	.num_controls = ARRAY_SIZE(tegrat186_dspk_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static bool tegra186_dspk_wr_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	case TEGRA186_DSPK_RX_INT_MASK ... TEGRA186_DSPK_RX_CIF_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	case TEGRA186_DSPK_ENABLE ... TEGRA186_DSPK_CG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	case TEGRA186_DSPK_CORE_CTRL ... TEGRA186_DSPK_CODEC_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static bool tegra186_dspk_rd_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	if (tegra186_dspk_wr_reg(dev, reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	case TEGRA186_DSPK_RX_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	case TEGRA186_DSPK_RX_INT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	case TEGRA186_DSPK_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	case TEGRA186_DSPK_INT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static bool tegra186_dspk_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	case TEGRA186_DSPK_RX_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	case TEGRA186_DSPK_RX_INT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	case TEGRA186_DSPK_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	case TEGRA186_DSPK_INT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const struct regmap_config tegra186_dspk_regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	.reg_bits		= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	.reg_stride		= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	.val_bits		= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	.max_register		= TEGRA186_DSPK_CODEC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	.writeable_reg		= tegra186_dspk_wr_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	.readable_reg		= tegra186_dspk_rd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	.volatile_reg		= tegra186_dspk_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	.reg_defaults		= tegra186_dspk_reg_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	.num_reg_defaults	= ARRAY_SIZE(tegra186_dspk_reg_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	.cache_type		= REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static const struct of_device_id tegra186_dspk_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	{ .compatible = "nvidia,tegra186-dspk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MODULE_DEVICE_TABLE(of, tegra186_dspk_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int tegra186_dspk_platform_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	struct tegra186_dspk *dspk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	dspk = devm_kzalloc(dev, sizeof(*dspk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	if (!dspk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	dspk->osr_val = DSPK_OSR_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	dspk->lrsel = DSPK_LRSEL_LEFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	dspk->ch_sel = DSPK_CH_SELECT_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	dspk->mono_to_stereo = 0; /* "Zero" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	dev_set_drvdata(dev, dspk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	dspk->clk_dspk = devm_clk_get(dev, "dspk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	if (IS_ERR(dspk->clk_dspk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		dev_err(dev, "can't retrieve DSPK clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 		return PTR_ERR(dspk->clk_dspk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 		return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	dspk->regmap = devm_regmap_init_mmio(dev, regs, &tegra186_dspk_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	if (IS_ERR(dspk->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 		dev_err(dev, "regmap init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 		return PTR_ERR(dspk->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	regcache_cache_only(dspk->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	err = devm_snd_soc_register_component(dev, &tegra186_dspk_cmpnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 					      tegra186_dspk_dais,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 					      ARRAY_SIZE(tegra186_dspk_dais));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		dev_err(dev, "can't register DSPK component, err: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 			err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int tegra186_dspk_platform_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const struct dev_pm_ops tegra186_dspk_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	SET_RUNTIME_PM_OPS(tegra186_dspk_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 			   tegra186_dspk_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 				pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static struct platform_driver tegra186_dspk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 		.name = "tegra186-dspk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 		.of_match_table = tegra186_dspk_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 		.pm = &tegra186_dspk_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	.probe = tegra186_dspk_platform_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	.remove = tegra186_dspk_platform_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) module_platform_driver(tegra186_dspk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MODULE_AUTHOR("Mohan Kumar <mkumard@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) MODULE_AUTHOR("Sameer Pujar <spujar@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) MODULE_DESCRIPTION("Tegra186 ASoC DSPK driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) MODULE_LICENSE("GPL v2");