^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This driver provides regmap to access to analog part of audio codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * found on Allwinner A23, A31s, A33, H3 and A64 Socs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2016 Chen-Yu Tsai <wens@csie.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "sun8i-adda-pr-regmap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Analog control register access bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ADDA_PR 0x0 /* PRCM base + 0x1c0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ADDA_PR_RESET BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ADDA_PR_WRITE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ADDA_PR_ADDR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ADDA_PR_ADDR_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ADDA_PR_DATA_IN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ADDA_PR_DATA_IN_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ADDA_PR_DATA_OUT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ADDA_PR_DATA_OUT_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* regmap access bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int adda_reg_read(void *context, unsigned int reg, unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void __iomem *base = (void __iomem *)context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* De-assert reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) writel(readl(base) | ADDA_PR_RESET, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Clear write bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) writel(readl(base) & ~ADDA_PR_WRITE, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Set register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) tmp = readl(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) tmp &= ~(ADDA_PR_ADDR_MASK << ADDA_PR_ADDR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) writel(tmp, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Read back value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *val = readl(base) & ADDA_PR_DATA_OUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int adda_reg_write(void *context, unsigned int reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void __iomem *base = (void __iomem *)context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* De-assert reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) writel(readl(base) | ADDA_PR_RESET, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Set register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) tmp = readl(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) tmp &= ~(ADDA_PR_ADDR_MASK << ADDA_PR_ADDR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) writel(tmp, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Set data to write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) tmp = readl(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) tmp &= ~(ADDA_PR_DATA_IN_MASK << ADDA_PR_DATA_IN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) tmp |= (val & ADDA_PR_DATA_IN_MASK) << ADDA_PR_DATA_IN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) writel(tmp, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Set write bit to signal a write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) writel(readl(base) | ADDA_PR_WRITE, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Clear write bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) writel(readl(base) & ~ADDA_PR_WRITE, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct regmap_config adda_pr_regmap_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .name = "adda-pr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .reg_bits = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .reg_stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .reg_read = adda_reg_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .reg_write = adda_reg_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .max_register = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct regmap *sun8i_adda_pr_regmap_init(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return devm_regmap_init(dev, NULL, base, &adda_pr_regmap_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) EXPORT_SYMBOL_GPL(sun8i_adda_pr_regmap_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MODULE_DESCRIPTION("Allwinner analog audio codec regmap driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MODULE_AUTHOR("Vasily Khoruzhick <anarsoul@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MODULE_ALIAS("platform:sunxi-adda-pr");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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