^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA SoC SPDIF Audio Layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2015 Andrea Venturi <be17068@iperbole.bo.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2015 Marcus Cooper <codekipper@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on the Allwinner SDK driver, released under the GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SUN4I_SPDIF_CTL (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SUN4I_SPDIF_CTL_MCLKDIV(v) ((v) << 4) /* v even */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SUN4I_SPDIF_CTL_MCLKOUTEN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SUN4I_SPDIF_CTL_GEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SUN4I_SPDIF_CTL_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SUN4I_SPDIF_TXCFG (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SUN4I_SPDIF_TXCFG_SINGLEMOD BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SUN4I_SPDIF_TXCFG_ASS BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SUN4I_SPDIF_TXCFG_NONAUDIO BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SUN4I_SPDIF_TXCFG_TXRATIO(v) ((v) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SUN4I_SPDIF_TXCFG_TXRATIO_MASK GENMASK(8, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SUN4I_SPDIF_TXCFG_FMTRVD GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SUN4I_SPDIF_TXCFG_FMT16BIT (0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SUN4I_SPDIF_TXCFG_FMT20BIT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SUN4I_SPDIF_TXCFG_FMT24BIT (2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SUN4I_SPDIF_TXCFG_CHSTMODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SUN4I_SPDIF_TXCFG_TXEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SUN4I_SPDIF_RXCFG (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SUN4I_SPDIF_RXCFG_LOCKFLAG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SUN4I_SPDIF_RXCFG_CHSTSRC BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SUN4I_SPDIF_RXCFG_CHSTCP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SUN4I_SPDIF_RXCFG_RXEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SUN4I_SPDIF_TXFIFO (0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SUN4I_SPDIF_RXFIFO (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SUN4I_SPDIF_FCTL (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SUN4I_SPDIF_FCTL_FIFOSRC BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SUN4I_SPDIF_FCTL_FTX BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SUN4I_SPDIF_FCTL_FRX BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SUN4I_SPDIF_FCTL_TXTL(v) ((v) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SUN4I_SPDIF_FCTL_TXTL_MASK GENMASK(12, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SUN4I_SPDIF_FCTL_RXTL(v) ((v) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SUN4I_SPDIF_FCTL_RXTL_MASK GENMASK(7, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SUN4I_SPDIF_FCTL_TXIM BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SUN4I_SPDIF_FCTL_RXOM(v) ((v) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SUN4I_SPDIF_FCTL_RXOM_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SUN50I_H6_SPDIF_FCTL (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SUN50I_H6_SPDIF_FCTL_HUB_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SUN50I_H6_SPDIF_FCTL_FTX BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SUN50I_H6_SPDIF_FCTL_FRX BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SUN50I_H6_SPDIF_FCTL_TXTL(v) ((v) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SUN50I_H6_SPDIF_FCTL_TXTL_MASK GENMASK(19, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SUN50I_H6_SPDIF_FCTL_RXTL(v) ((v) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SUN50I_H6_SPDIF_FCTL_RXTL_MASK GENMASK(10, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SUN50I_H6_SPDIF_FCTL_TXIM BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SUN50I_H6_SPDIF_FCTL_RXOM(v) ((v) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SUN50I_H6_SPDIF_FCTL_RXOM_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SUN4I_SPDIF_FSTA (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SUN4I_SPDIF_FSTA_TXE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SUN4I_SPDIF_FSTA_TXECNTSHT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SUN4I_SPDIF_FSTA_RXA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SUN4I_SPDIF_FSTA_RXACNTSHT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SUN4I_SPDIF_INT (0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SUN4I_SPDIF_INT_RXLOCKEN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SUN4I_SPDIF_INT_RXUNLOCKEN BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SUN4I_SPDIF_INT_RXPARERREN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SUN4I_SPDIF_INT_TXDRQEN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SUN4I_SPDIF_INT_TXUIEN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SUN4I_SPDIF_INT_TXOIEN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SUN4I_SPDIF_INT_TXEIEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SUN4I_SPDIF_INT_RXDRQEN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SUN4I_SPDIF_INT_RXOIEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SUN4I_SPDIF_INT_RXAIEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SUN4I_SPDIF_ISTA (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SUN4I_SPDIF_ISTA_RXLOCKSTA BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SUN4I_SPDIF_ISTA_RXUNLOCKSTA BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SUN4I_SPDIF_ISTA_RXPARERRSTA BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SUN4I_SPDIF_ISTA_TXUSTA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SUN4I_SPDIF_ISTA_TXOSTA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SUN4I_SPDIF_ISTA_TXESTA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SUN4I_SPDIF_ISTA_RXOSTA BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SUN4I_SPDIF_ISTA_RXASTA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SUN8I_SPDIF_TXFIFO (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SUN4I_SPDIF_TXCNT (0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SUN4I_SPDIF_RXCNT (0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SUN4I_SPDIF_TXCHSTA0 (0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SUN4I_SPDIF_TXCHSTA0_CLK(v) ((v) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SUN4I_SPDIF_TXCHSTA0_SAMFREQ(v) ((v) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SUN4I_SPDIF_TXCHSTA0_SAMFREQ_MASK GENMASK(27, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SUN4I_SPDIF_TXCHSTA0_CHNUM(v) ((v) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SUN4I_SPDIF_TXCHSTA0_CHNUM_MASK GENMASK(23, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SUN4I_SPDIF_TXCHSTA0_SRCNUM(v) ((v) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SUN4I_SPDIF_TXCHSTA0_CATACOD(v) ((v) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SUN4I_SPDIF_TXCHSTA0_MODE(v) ((v) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SUN4I_SPDIF_TXCHSTA0_EMPHASIS(v) ((v) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SUN4I_SPDIF_TXCHSTA0_CP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SUN4I_SPDIF_TXCHSTA0_AUDIO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SUN4I_SPDIF_TXCHSTA0_PRO BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SUN4I_SPDIF_TXCHSTA1 (0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SUN4I_SPDIF_TXCHSTA1_CGMSA(v) ((v) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ(v) ((v) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SUN4I_SPDIF_TXCHSTA1_SAMWORDLEN(v) ((v) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SUN4I_SPDIF_TXCHSTA1_MAXWORDLEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SUN4I_SPDIF_RXCHSTA0 (0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SUN4I_SPDIF_RXCHSTA0_CLK(v) ((v) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SUN4I_SPDIF_RXCHSTA0_SAMFREQ(v) ((v) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SUN4I_SPDIF_RXCHSTA0_CHNUM(v) ((v) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SUN4I_SPDIF_RXCHSTA0_SRCNUM(v) ((v) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SUN4I_SPDIF_RXCHSTA0_CATACOD(v) ((v) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SUN4I_SPDIF_RXCHSTA0_MODE(v) ((v) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SUN4I_SPDIF_RXCHSTA0_EMPHASIS(v) ((v) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SUN4I_SPDIF_RXCHSTA0_CP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SUN4I_SPDIF_RXCHSTA0_AUDIO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SUN4I_SPDIF_RXCHSTA0_PRO BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SUN4I_SPDIF_RXCHSTA1 (0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SUN4I_SPDIF_RXCHSTA1_CGMSA(v) ((v) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SUN4I_SPDIF_RXCHSTA1_ORISAMFREQ(v) ((v) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SUN4I_SPDIF_RXCHSTA1_SAMWORDLEN(v) ((v) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SUN4I_SPDIF_RXCHSTA1_MAXWORDLEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Defines for Sampling Frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SUN4I_SPDIF_SAMFREQ_44_1KHZ 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SUN4I_SPDIF_SAMFREQ_NOT_INDICATED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SUN4I_SPDIF_SAMFREQ_48KHZ 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SUN4I_SPDIF_SAMFREQ_32KHZ 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SUN4I_SPDIF_SAMFREQ_22_05KHZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SUN4I_SPDIF_SAMFREQ_24KHZ 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SUN4I_SPDIF_SAMFREQ_88_2KHZ 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SUN4I_SPDIF_SAMFREQ_76_8KHZ 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SUN4I_SPDIF_SAMFREQ_96KHZ 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SUN4I_SPDIF_SAMFREQ_176_4KHZ 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SUN4I_SPDIF_SAMFREQ_192KHZ 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * struct sun4i_spdif_quirks - Differences between SoC variants.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @reg_dac_txdata: TX FIFO offset for DMA config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @has_reset: SoC needs reset deasserted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @val_fctl_ftx: TX FIFO flush bitmask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct sun4i_spdif_quirks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned int reg_dac_txdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) bool has_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int val_fctl_ftx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct sun4i_spdif_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct clk *spdif_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct clk *apb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct snd_soc_dai_driver cpu_dai_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct snd_dmaengine_dai_dma_data dma_params_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) const struct sun4i_spdif_quirks *quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void sun4i_spdif_configure(struct sun4i_spdif_dev *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) const struct sun4i_spdif_quirks *quirks = host->quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* soft reset SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) regmap_write(host->regmap, SUN4I_SPDIF_CTL, SUN4I_SPDIF_CTL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* flush TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) quirks->val_fctl_ftx, quirks->val_fctl_ftx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* clear TX counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) regmap_write(host->regmap, SUN4I_SPDIF_TXCNT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void sun4i_snd_txctrl_on(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct sun4i_spdif_dev *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (substream->runtime->channels == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) SUN4I_SPDIF_TXCFG_SINGLEMOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) SUN4I_SPDIF_TXCFG_SINGLEMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* SPDIF TX ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) SUN4I_SPDIF_TXCFG_TXEN, SUN4I_SPDIF_TXCFG_TXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* DRQ ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) regmap_update_bits(host->regmap, SUN4I_SPDIF_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) SUN4I_SPDIF_INT_TXDRQEN, SUN4I_SPDIF_INT_TXDRQEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Global enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) regmap_update_bits(host->regmap, SUN4I_SPDIF_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) SUN4I_SPDIF_CTL_GEN, SUN4I_SPDIF_CTL_GEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void sun4i_snd_txctrl_off(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct sun4i_spdif_dev *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* SPDIF TX DISABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) SUN4I_SPDIF_TXCFG_TXEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* DRQ DISABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) regmap_update_bits(host->regmap, SUN4I_SPDIF_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) SUN4I_SPDIF_INT_TXDRQEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Global disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) regmap_update_bits(host->regmap, SUN4I_SPDIF_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) SUN4I_SPDIF_CTL_GEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int sun4i_spdif_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) sun4i_spdif_configure(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned long rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 mclk_div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int mclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct platform_device *pdev = host->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Add the PCM and raw data select interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) switch (params_channels(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case 1: /* PCM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) fmt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case 4: /* raw data mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) fmt = SUN4I_SPDIF_TXCFG_NONAUDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) fmt |= SUN4I_SPDIF_TXCFG_FMT16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) case SNDRV_PCM_FORMAT_S20_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) fmt |= SUN4I_SPDIF_TXCFG_FMT20BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case SNDRV_PCM_FORMAT_S24_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) fmt |= SUN4I_SPDIF_TXCFG_FMT24BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case 22050:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case 176400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) mclk = 22579200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case 24000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mclk = 24576000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = clk_set_rate(host->spdif_clk, mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "Setting SPDIF clock rate for %d Hz failed!\n", mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) SUN4I_SPDIF_FCTL_TXIM, SUN4I_SPDIF_FCTL_TXIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case 22050:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case 24000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) mclk_div = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) mclk_div = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) mclk_div = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) mclk_div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case 176400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mclk_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) reg_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) reg_val |= SUN4I_SPDIF_TXCFG_ASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) reg_val |= fmt; /* set non audio and bit depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) reg_val |= SUN4I_SPDIF_TXCFG_CHSTMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) reg_val |= SUN4I_SPDIF_TXCFG_TXRATIO(mclk_div - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) regmap_write(host->regmap, SUN4I_SPDIF_TXCFG, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int sun4i_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) sun4i_snd_txctrl_on(substream, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) sun4i_snd_txctrl_off(substream, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int sun4i_spdif_soc_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) snd_soc_dai_init_dma_data(dai, &host->dma_params_tx, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const struct snd_soc_dai_ops sun4i_spdif_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .startup = sun4i_spdif_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .trigger = sun4i_spdif_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .hw_params = sun4i_spdif_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const struct regmap_config sun4i_spdif_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .max_register = SUN4I_SPDIF_RXCHSTA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define SUN4I_RATES SNDRV_PCM_RATE_8000_192000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define SUN4I_FORMATS (SNDRV_PCM_FORMAT_S16_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) SNDRV_PCM_FORMAT_S20_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) SNDRV_PCM_FORMAT_S24_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct snd_soc_dai_driver sun4i_spdif_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .rates = SUN4I_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .formats = SUN4I_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .probe = sun4i_spdif_soc_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .ops = &sun4i_spdif_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .name = "spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const struct sun4i_spdif_quirks sun4i_a10_spdif_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .reg_dac_txdata = SUN4I_SPDIF_TXFIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const struct sun4i_spdif_quirks sun6i_a31_spdif_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .reg_dac_txdata = SUN4I_SPDIF_TXFIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .has_reset = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const struct sun4i_spdif_quirks sun8i_h3_spdif_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .has_reset = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .val_fctl_ftx = SUN50I_H6_SPDIF_FCTL_FTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .has_reset = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static const struct of_device_id sun4i_spdif_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .compatible = "allwinner,sun4i-a10-spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .data = &sun4i_a10_spdif_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .compatible = "allwinner,sun6i-a31-spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .data = &sun6i_a31_spdif_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .compatible = "allwinner,sun8i-h3-spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .data = &sun8i_h3_spdif_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .compatible = "allwinner,sun50i-h6-spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .data = &sun50i_h6_spdif_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MODULE_DEVICE_TABLE(of, sun4i_spdif_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static const struct snd_soc_component_driver sun4i_spdif_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .name = "sun4i-spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int sun4i_spdif_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct sun4i_spdif_dev *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) clk_disable_unprepare(host->spdif_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) clk_disable_unprepare(host->apb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int sun4i_spdif_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct sun4i_spdif_dev *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = clk_prepare_enable(host->spdif_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = clk_prepare_enable(host->apb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) clk_disable_unprepare(host->spdif_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static int sun4i_spdif_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct sun4i_spdif_dev *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) const struct sun4i_spdif_quirks *quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_dbg(&pdev->dev, "Entered %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) host->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Initialize this copy of the CPU DAI driver structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) memcpy(&host->cpu_dai_drv, &sun4i_spdif_dai, sizeof(sun4i_spdif_dai));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) host->cpu_dai_drv.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* Get the addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) quirks = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (quirks == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) host->quirks = quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) host->regmap = devm_regmap_init_mmio(&pdev->dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) &sun4i_spdif_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) host->apb_clk = devm_clk_get(&pdev->dev, "apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (IS_ERR(host->apb_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dev_err(&pdev->dev, "failed to get a apb clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return PTR_ERR(host->apb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) host->spdif_clk = devm_clk_get(&pdev->dev, "spdif");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (IS_ERR(host->spdif_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dev_err(&pdev->dev, "failed to get a spdif clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return PTR_ERR(host->spdif_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) host->dma_params_tx.addr = res->start + quirks->reg_dac_txdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) host->dma_params_tx.maxburst = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) host->dma_params_tx.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) platform_set_drvdata(pdev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (quirks->has_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) host->rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (PTR_ERR(host->rst) == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dev_err(&pdev->dev, "Failed to get reset: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (!IS_ERR(host->rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) reset_control_deassert(host->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) &sun4i_spdif_component, &sun4i_spdif_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (!pm_runtime_enabled(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret = sun4i_spdif_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) goto err_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) err_suspend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) sun4i_spdif_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) err_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int sun4i_spdif_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) sun4i_spdif_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const struct dev_pm_ops sun4i_spdif_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) SET_RUNTIME_PM_OPS(sun4i_spdif_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) sun4i_spdif_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static struct platform_driver sun4i_spdif_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .name = "sun4i-spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .of_match_table = of_match_ptr(sun4i_spdif_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .pm = &sun4i_spdif_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .probe = sun4i_spdif_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .remove = sun4i_spdif_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) module_platform_driver(sun4i_spdif_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) MODULE_AUTHOR("Marcus Cooper <codekipper@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) MODULE_DESCRIPTION("Allwinner sun4i SPDIF SoC Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) MODULE_ALIAS("platform:sun4i-spdif");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags