^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 Andrea Venturi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Andrea Venturi <be17068@iperbole.bo.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2016 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SUN4I_I2S_CTRL_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SUN4I_I2S_CTRL_SDO_EN_MASK GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SUN4I_I2S_CTRL_SDO_EN(sdo) BIT(8 + (sdo))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SUN4I_I2S_CTRL_MODE_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SUN4I_I2S_CTRL_MODE_SLAVE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SUN4I_I2S_CTRL_MODE_MASTER (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SUN4I_I2S_CTRL_TX_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SUN4I_I2S_CTRL_RX_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SUN4I_I2S_CTRL_GL_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SUN4I_I2S_FMT0_REG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SUN4I_I2S_FMT0_SR_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SUN4I_I2S_FMT0_SR(sr) ((sr) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SUN4I_I2S_FMT0_WSS_MASK GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SUN4I_I2S_FMT0_WSS(wss) ((wss) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SUN4I_I2S_FMT0_FMT_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SUN4I_I2S_FMT1_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SUN4I_I2S_FIFO_TX_REG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SUN4I_I2S_FIFO_RX_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SUN4I_I2S_FIFO_CTRL_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SUN4I_I2S_FIFO_CTRL_FLUSH_TX BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SUN4I_I2S_FIFO_CTRL_FLUSH_RX BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode) ((mode) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode) (mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SUN4I_I2S_FIFO_STA_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SUN4I_I2S_DMA_INT_CTRL_REG 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SUN4I_I2S_INT_STA_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SUN4I_I2S_CLK_DIV_REG 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SUN4I_I2S_CLK_DIV_MCLK_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SUN4I_I2S_CLK_DIV_BCLK_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SUN4I_I2S_CLK_DIV_BCLK(bclk) ((bclk) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SUN4I_I2S_CLK_DIV_MCLK_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SUN4I_I2S_CLK_DIV_MCLK(mclk) ((mclk) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SUN4I_I2S_TX_CNT_REG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SUN4I_I2S_RX_CNT_REG 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SUN4I_I2S_TX_CHAN_SEL_REG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SUN4I_I2S_CHAN_SEL_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SUN4I_I2S_TX_CHAN_MAP_REG 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SUN4I_I2S_TX_CHAN_MAP(chan, sample) ((sample) << (chan << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SUN4I_I2S_RX_CHAN_SEL_REG 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SUN4I_I2S_RX_CHAN_MAP_REG 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Defines required for sun8i-h3 support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SUN8I_I2S_CTRL_BCLK_OUT BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SUN8I_I2S_CTRL_LRCK_OUT BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SUN8I_I2S_CTRL_MODE_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SUN8I_I2S_CTRL_MODE_RIGHT (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SUN8I_I2S_CTRL_MODE_LEFT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SUN8I_I2S_CTRL_MODE_PCM (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SUN8I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SUN8I_I2S_FMT0_BCLK_POLARITY_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SUN8I_I2S_INT_STA_REG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SUN8I_I2S_FIFO_TX_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SUN8I_I2S_CHAN_CFG_REG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SUN8I_I2S_TX_CHAN_MAP_REG 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SUN8I_I2S_TX_CHAN_SEL_REG 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SUN8I_I2S_RX_CHAN_SEL_REG 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SUN8I_I2S_RX_CHAN_MAP_REG 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct sun4i_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * struct sun4i_i2s_quirks - Differences between SoC variants.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @has_reset: SoC needs reset deasserted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @reg_offset_txdata: offset of the tx fifo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @sun4i_i2s_regmap: regmap config to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @field_clkdiv_mclk_en: regmap field to enable mclk output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @field_fmt_wss: regmap field to set word select size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @field_fmt_sr: regmap field to set sample resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @bclk_dividers: bit clock dividers array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @num_bclk_dividers: number of bit clock dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @mclk_dividers: mclk dividers array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @num_mclk_dividers: number of mclk dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @get_bclk_parent_rate: callback to get bclk parent rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @get_sr: callback to get sample resolution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @get_wss: callback to get word select size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @set_chan_cfg: callback to set channel configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @set_fmt: callback to set format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct sun4i_i2s_quirks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bool has_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int reg_offset_txdata; /* TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const struct regmap_config *sun4i_i2s_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Register fields for i2s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct reg_field field_clkdiv_mclk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct reg_field field_fmt_wss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct reg_field field_fmt_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) const struct sun4i_i2s_clk_div *bclk_dividers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int num_bclk_dividers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) const struct sun4i_i2s_clk_div *mclk_dividers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int num_mclk_dividers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) s8 (*get_sr)(const struct sun4i_i2s *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) s8 (*get_wss)(const struct sun4i_i2s *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int (*set_chan_cfg)(const struct sun4i_i2s *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) const struct snd_pcm_hw_params *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int (*set_fmt)(const struct sun4i_i2s *, unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct sun4i_i2s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct clk *bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct clk *mod_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned int format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int mclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct snd_dmaengine_dai_dma_data capture_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct snd_dmaengine_dai_dma_data playback_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Register fields for i2s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct regmap_field *field_clkdiv_mclk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct regmap_field *field_fmt_wss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct regmap_field *field_fmt_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) const struct sun4i_i2s_quirks *variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct sun4i_i2s_clk_div {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u8 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { .div = 2, .val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { .div = 4, .val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { .div = 6, .val = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { .div = 8, .val = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { .div = 12, .val = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { .div = 16, .val = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* TODO - extend divide ratio supported by newer SoCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { .div = 1, .val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { .div = 2, .val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { .div = 4, .val = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { .div = 6, .val = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { .div = 8, .val = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { .div = 12, .val = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { .div = 16, .val = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { .div = 24, .val = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* TODO - extend divide ratio supported by newer SoCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct sun4i_i2s_clk_div sun8i_i2s_clk_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { .div = 1, .val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { .div = 2, .val = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { .div = 4, .val = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { .div = 6, .val = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { .div = 8, .val = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { .div = 12, .val = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { .div = 16, .val = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { .div = 24, .val = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { .div = 32, .val = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { .div = 48, .val = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { .div = 64, .val = 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { .div = 96, .val = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { .div = 128, .val = 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { .div = 176, .val = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { .div = 192, .val = 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static unsigned long sun4i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return i2s->mclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static unsigned long sun8i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return clk_get_rate(i2s->mod_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int sampling_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned int channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned int word_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) const struct sun4i_i2s_clk_div *dividers = i2s->variant->bclk_dividers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int div = parent_rate / sampling_rate / word_size / channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) for (i = 0; i < i2s->variant->num_bclk_dividers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) const struct sun4i_i2s_clk_div *bdiv = ÷rs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (bdiv->div == div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return bdiv->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned long mclk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) const struct sun4i_i2s_clk_div *dividers = i2s->variant->mclk_dividers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int div = parent_rate / mclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) for (i = 0; i < i2s->variant->num_mclk_dividers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) const struct sun4i_i2s_clk_div *mdiv = ÷rs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (mdiv->div == div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return mdiv->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int sun4i_i2s_oversample_rates[] = { 128, 192, 256, 384, 512, 768 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static bool sun4i_i2s_oversample_is_valid(unsigned int oversample)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (sun4i_i2s_oversample_rates[i] == oversample)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned int slots,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int oversample_rate, clk_rate, bclk_parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int bclk_div, mclk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) case 176400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) case 22050:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case 11025:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) clk_rate = 22579200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case 128000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case 64000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case 24000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) case 12000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) clk_rate = 24576000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev_err(dai->dev, "Unsupported sample rate: %u\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = clk_set_rate(i2s->mod_clk, clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) oversample_rate = i2s->mclk_freq / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (!sun4i_i2s_oversample_is_valid(oversample_rate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev_err(dai->dev, "Unsupported oversample rate: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) oversample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) bclk_parent_rate = i2s->variant->get_bclk_parent_rate(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) bclk_div = sun4i_i2s_get_bclk_div(i2s, bclk_parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) rate, slots, slot_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (bclk_div < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) mclk_div = sun4i_i2s_get_mclk_div(i2s, clk_rate, i2s->mclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (mclk_div < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) SUN4I_I2S_CLK_DIV_BCLK(bclk_div) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) SUN4I_I2S_CLK_DIV_MCLK(mclk_div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static s8 sun4i_i2s_get_sr(const struct sun4i_i2s *i2s, int width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (width < 16 || width > 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (width % 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return (width - 16) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static s8 sun4i_i2s_get_wss(const struct sun4i_i2s *i2s, int width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (width < 16 || width > 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (width % 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return (width - 16) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static s8 sun8i_i2s_get_sr_wss(const struct sun4i_i2s *i2s, int width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (width % 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (width < 8 || width > 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return (width - 8) / 4 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int sun4i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) const struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned int channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Map the channels for playback and capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Configure the channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) regmap_update_bits(i2s->regmap, SUN4I_I2S_TX_CHAN_SEL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) SUN4I_I2S_CHAN_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) SUN4I_I2S_CHAN_SEL(channels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) regmap_update_bits(i2s->regmap, SUN4I_I2S_RX_CHAN_SEL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) SUN4I_I2S_CHAN_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) SUN4I_I2S_CHAN_SEL(channels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) const struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned int channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned int slots = channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned int lrck_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (i2s->slots)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) slots = i2s->slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Map the channels for playback and capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Configure the channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) SUN4I_I2S_CHAN_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) SUN4I_I2S_CHAN_SEL(channels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) SUN4I_I2S_CHAN_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) SUN4I_I2S_CHAN_SEL(channels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case SND_SOC_DAIFMT_DSP_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) lrck_period = params_physical_width(params) * slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case SND_SOC_DAIFMT_RIGHT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) lrck_period = params_physical_width(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) SUN8I_I2S_TX_CHAN_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) SUN8I_I2S_TX_CHAN_EN(channels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unsigned int word_size = params_width(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned int slot_width = params_physical_width(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned int channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) unsigned int slots = channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int ret, sr, wss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (i2s->slots)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) slots = i2s->slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (i2s->slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) slot_width = i2s->slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ret = i2s->variant->set_chan_cfg(i2s, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_err(dai->dev, "Invalid channel configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) switch (params_physical_width(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) width = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dev_err(dai->dev, "Unsupported physical sample width: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) params_physical_width(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) i2s->playback_dma_data.addr_width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) sr = i2s->variant->get_sr(i2s, word_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (sr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) wss = i2s->variant->get_wss(i2s, slot_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (wss < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) regmap_field_write(i2s->field_fmt_wss, wss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) regmap_field_write(i2s->field_fmt_sr, sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return sun4i_i2s_set_clk_rate(dai, params_rate(params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) slots, slot_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* DAI clock polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Invert both clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* Invert bit clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* Invert frame clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) val = SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) SUN4I_I2S_FMT0_BCLK_POLARITY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* DAI Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) val = SUN4I_I2S_FMT0_FMT_I2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) val = SUN4I_I2S_FMT0_FMT_LEFT_J;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case SND_SOC_DAIFMT_RIGHT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) val = SUN4I_I2S_FMT0_FMT_RIGHT_J;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) SUN4I_I2S_FMT0_FMT_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* DAI clock master masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* BCLK and LRCLK master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) val = SUN4I_I2S_CTRL_MODE_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* BCLK and LRCLK slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) val = SUN4I_I2S_CTRL_MODE_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) SUN4I_I2S_CTRL_MODE_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u32 mode, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u8 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * DAI clock polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * The setup for LRCK contradicts the datasheet, but under a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * scope it's clear that the LRCK polarity is reversed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * compared to the expected polarity on the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* Invert both clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Invert bit clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Invert frame clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) SUN8I_I2S_FMT0_BCLK_POLARITY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* DAI Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) mode = SUN8I_I2S_CTRL_MODE_PCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) offset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) case SND_SOC_DAIFMT_DSP_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) mode = SUN8I_I2S_CTRL_MODE_PCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) mode = SUN8I_I2S_CTRL_MODE_LEFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) offset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) mode = SUN8I_I2S_CTRL_MODE_LEFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case SND_SOC_DAIFMT_RIGHT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) mode = SUN8I_I2S_CTRL_MODE_RIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) SUN8I_I2S_CTRL_MODE_MASK, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) SUN8I_I2S_TX_CHAN_OFFSET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) SUN8I_I2S_TX_CHAN_OFFSET(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) SUN8I_I2S_TX_CHAN_OFFSET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) SUN8I_I2S_TX_CHAN_OFFSET(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* DAI clock master masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* BCLK and LRCLK master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) val = SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* BCLK and LRCLK slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ret = i2s->variant->set_fmt(i2s, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dev_err(dai->dev, "Unsupported format configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* Set significant bits in our FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) i2s->format = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* Flush RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) SUN4I_I2S_FIFO_CTRL_FLUSH_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) SUN4I_I2S_FIFO_CTRL_FLUSH_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* Clear RX counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* Enable RX Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) SUN4I_I2S_CTRL_RX_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) SUN4I_I2S_CTRL_RX_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* Enable RX DRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Flush TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) SUN4I_I2S_FIFO_CTRL_FLUSH_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) SUN4I_I2S_FIFO_CTRL_FLUSH_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* Clear TX counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* Enable TX Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) SUN4I_I2S_CTRL_TX_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) SUN4I_I2S_CTRL_TX_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Enable TX DRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static void sun4i_i2s_stop_capture(struct sun4i_i2s *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* Disable RX Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) SUN4I_I2S_CTRL_RX_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* Disable RX DRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static void sun4i_i2s_stop_playback(struct sun4i_i2s *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* Disable TX Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) SUN4I_I2S_CTRL_TX_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* Disable TX DRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static int sun4i_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) sun4i_i2s_start_playback(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) sun4i_i2s_start_capture(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) sun4i_i2s_stop_playback(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) sun4i_i2s_stop_capture(i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (clk_id != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) i2s->mclk_freq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int sun4i_i2s_set_tdm_slot(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) unsigned int tx_mask, unsigned int rx_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) int slots, int slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (slots > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) i2s->slots = slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) i2s->slot_width = slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .hw_params = sun4i_i2s_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .set_fmt = sun4i_i2s_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .set_sysclk = sun4i_i2s_set_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .set_tdm_slot = sun4i_i2s_set_tdm_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .trigger = sun4i_i2s_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) snd_soc_dai_init_dma_data(dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) &i2s->playback_dma_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) &i2s->capture_dma_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) snd_soc_dai_set_drvdata(dai, i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static struct snd_soc_dai_driver sun4i_i2s_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .probe = sun4i_i2s_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .stream_name = "Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .stream_name = "Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .ops = &sun4i_i2s_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .symmetric_rates = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static const struct snd_soc_component_driver sun4i_i2s_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .name = "sun4i-dai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) case SUN4I_I2S_FIFO_TX_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) case SUN4I_I2S_FIFO_RX_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) case SUN4I_I2S_FIFO_STA_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) case SUN4I_I2S_FIFO_RX_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) case SUN4I_I2S_INT_STA_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) case SUN4I_I2S_RX_CNT_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) case SUN4I_I2S_TX_CNT_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) case SUN8I_I2S_FIFO_TX_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (reg == SUN8I_I2S_INT_STA_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (reg == SUN8I_I2S_FIFO_TX_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return sun4i_i2s_volatile_reg(dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static const struct reg_default sun4i_i2s_reg_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) { SUN4I_I2S_CTRL_REG, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) { SUN4I_I2S_FMT0_REG, 0x0000000c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) { SUN4I_I2S_FMT1_REG, 0x00004020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) { SUN4I_I2S_TX_CHAN_SEL_REG, 0x00000001 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) { SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) { SUN4I_I2S_RX_CHAN_SEL_REG, 0x00000001 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) { SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static const struct reg_default sun8i_i2s_reg_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) { SUN4I_I2S_CTRL_REG, 0x00060000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) { SUN4I_I2S_FMT0_REG, 0x00000033 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) { SUN4I_I2S_FMT1_REG, 0x00000030 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) { SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) { SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static const struct regmap_config sun4i_i2s_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .max_register = SUN4I_I2S_RX_CHAN_MAP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .reg_defaults = sun4i_i2s_reg_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .num_reg_defaults = ARRAY_SIZE(sun4i_i2s_reg_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .writeable_reg = sun4i_i2s_wr_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .readable_reg = sun4i_i2s_rd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .volatile_reg = sun4i_i2s_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static const struct regmap_config sun8i_i2s_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .max_register = SUN8I_I2S_RX_CHAN_MAP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .reg_defaults = sun8i_i2s_reg_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .num_reg_defaults = ARRAY_SIZE(sun8i_i2s_reg_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .writeable_reg = sun4i_i2s_wr_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .readable_reg = sun8i_i2s_rd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .volatile_reg = sun8i_i2s_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static int sun4i_i2s_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct sun4i_i2s *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ret = clk_prepare_enable(i2s->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) dev_err(dev, "Failed to enable bus clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) regcache_cache_only(i2s->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) regcache_mark_dirty(i2s->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ret = regcache_sync(i2s->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dev_err(dev, "Failed to sync regmap cache\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /* Enable the whole hardware block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* Enable the first output line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) SUN4I_I2S_CTRL_SDO_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) SUN4I_I2S_CTRL_SDO_EN(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ret = clk_prepare_enable(i2s->mod_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) dev_err(dev, "Failed to enable module clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) clk_disable_unprepare(i2s->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static int sun4i_i2s_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct sun4i_i2s *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) clk_disable_unprepare(i2s->mod_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /* Disable our output lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) SUN4I_I2S_CTRL_SDO_EN_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* Disable the whole hardware block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) SUN4I_I2S_CTRL_GL_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) regcache_cache_only(i2s->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) clk_disable_unprepare(i2s->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .has_reset = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .bclk_dividers = sun4i_i2s_bclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .mclk_dividers = sun4i_i2s_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .get_sr = sun4i_i2s_get_sr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .get_wss = sun4i_i2s_get_wss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .set_chan_cfg = sun4i_i2s_set_chan_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .set_fmt = sun4i_i2s_set_soc_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .has_reset = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .bclk_dividers = sun4i_i2s_bclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .mclk_dividers = sun4i_i2s_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .get_sr = sun4i_i2s_get_sr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .get_wss = sun4i_i2s_get_wss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .set_chan_cfg = sun4i_i2s_set_chan_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .set_fmt = sun4i_i2s_set_soc_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * This doesn't describe the TDM controller documented in the A83t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * datasheet, but the three undocumented I2S controller that use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * older design.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .has_reset = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .bclk_dividers = sun4i_i2s_bclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .mclk_dividers = sun4i_i2s_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .get_sr = sun4i_i2s_get_sr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .get_wss = sun4i_i2s_get_wss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .set_chan_cfg = sun4i_i2s_set_chan_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .set_fmt = sun4i_i2s_set_soc_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .has_reset = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .sun4i_i2s_regmap = &sun8i_i2s_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .bclk_dividers = sun8i_i2s_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .mclk_dividers = sun8i_i2s_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .get_sr = sun8i_i2s_get_sr_wss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .get_wss = sun8i_i2s_get_sr_wss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .set_chan_cfg = sun8i_i2s_set_chan_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .set_fmt = sun8i_i2s_set_soc_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .has_reset = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .bclk_dividers = sun4i_i2s_bclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .mclk_dividers = sun4i_i2s_mclk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .get_sr = sun4i_i2s_get_sr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .get_wss = sun4i_i2s_get_wss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .set_chan_cfg = sun4i_i2s_set_chan_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .set_fmt = sun4i_i2s_set_soc_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static int sun4i_i2s_init_regmap_fields(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) struct sun4i_i2s *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) i2s->field_clkdiv_mclk_en =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) devm_regmap_field_alloc(dev, i2s->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) i2s->variant->field_clkdiv_mclk_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (IS_ERR(i2s->field_clkdiv_mclk_en))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) return PTR_ERR(i2s->field_clkdiv_mclk_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) i2s->field_fmt_wss =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) devm_regmap_field_alloc(dev, i2s->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) i2s->variant->field_fmt_wss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (IS_ERR(i2s->field_fmt_wss))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return PTR_ERR(i2s->field_fmt_wss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) i2s->field_fmt_sr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) devm_regmap_field_alloc(dev, i2s->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) i2s->variant->field_fmt_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (IS_ERR(i2s->field_fmt_sr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) return PTR_ERR(i2s->field_fmt_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static int sun4i_i2s_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) struct sun4i_i2s *i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (!i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) platform_set_drvdata(pdev, i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) i2s->variant = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (!i2s->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) i2s->bus_clk = devm_clk_get(&pdev->dev, "apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (IS_ERR(i2s->bus_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) dev_err(&pdev->dev, "Can't get our bus clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) return PTR_ERR(i2s->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) i2s->variant->sun4i_i2s_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (IS_ERR(i2s->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) dev_err(&pdev->dev, "Regmap initialisation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return PTR_ERR(i2s->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) i2s->mod_clk = devm_clk_get(&pdev->dev, "mod");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (IS_ERR(i2s->mod_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) dev_err(&pdev->dev, "Can't get our mod clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return PTR_ERR(i2s->mod_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (i2s->variant->has_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (IS_ERR(i2s->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) dev_err(&pdev->dev, "Failed to get reset control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return PTR_ERR(i2s->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (!IS_ERR(i2s->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) ret = reset_control_deassert(i2s->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) "Failed to deassert the reset control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) i2s->playback_dma_data.addr = res->start +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) i2s->variant->reg_offset_txdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) i2s->playback_dma_data.maxburst = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) i2s->capture_dma_data.maxburst = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (!pm_runtime_enabled(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) ret = sun4i_i2s_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) dev_err(&pdev->dev, "Could not initialise regmap fields\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) dev_err(&pdev->dev, "Could not register PCM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) &sun4i_i2s_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) &sun4i_i2s_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) dev_err(&pdev->dev, "Could not register DAI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) err_suspend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) sun4i_i2s_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (!IS_ERR(i2s->rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) reset_control_assert(i2s->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static int sun4i_i2s_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) sun4i_i2s_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (!IS_ERR(i2s->rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) reset_control_assert(i2s->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) static const struct of_device_id sun4i_i2s_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .compatible = "allwinner,sun4i-a10-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .data = &sun4i_a10_i2s_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .compatible = "allwinner,sun6i-a31-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .data = &sun6i_a31_i2s_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .compatible = "allwinner,sun8i-a83t-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .data = &sun8i_a83t_i2s_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .compatible = "allwinner,sun8i-h3-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .data = &sun8i_h3_i2s_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .compatible = "allwinner,sun50i-a64-codec-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .data = &sun50i_a64_codec_i2s_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) MODULE_DEVICE_TABLE(of, sun4i_i2s_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static const struct dev_pm_ops sun4i_i2s_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .runtime_resume = sun4i_i2s_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .runtime_suspend = sun4i_i2s_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static struct platform_driver sun4i_i2s_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .probe = sun4i_i2s_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .remove = sun4i_i2s_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .name = "sun4i-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .of_match_table = sun4i_i2s_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .pm = &sun4i_i2s_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) module_platform_driver(sun4i_i2s_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) MODULE_DESCRIPTION("Allwinner A10 I2S driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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