^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* SPDIF-rx Register Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define STM32_SPDIFRX_CR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STM32_SPDIFRX_IMR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STM32_SPDIFRX_SR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STM32_SPDIFRX_IFCR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define STM32_SPDIFRX_DR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define STM32_SPDIFRX_CSR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define STM32_SPDIFRX_DIR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define STM32_SPDIFRX_VERR 0x3F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define STM32_SPDIFRX_IDR 0x3F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define STM32_SPDIFRX_SIDR 0x3FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Bit definition for SPDIF_CR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPDIFRX_CR_SPDIFEN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPDIFRX_CR_RXDMAEN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPDIFRX_CR_RXSTEO BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPDIFRX_CR_DRFMT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPDIFRX_CR_PMSK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPDIFRX_CR_VMSK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPDIFRX_CR_CUMSK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPDIFRX_CR_PTMSK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPDIFRX_CR_CBDMAEN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPDIFRX_CR_CHSEL_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPDIFRX_CR_NBTR_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPDIFRX_CR_WFA BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPDIFRX_CR_INSEL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SPDIFRX_CR_CKSEN_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPDIFRX_CR_CKSEN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPDIFRX_CR_CKSBKPEN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Bit definition for SPDIFRX_IMR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SPDIFRX_IMR_RXNEI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SPDIFRX_IMR_CSRNEIE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SPDIFRX_IMR_PERRIE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SPDIFRX_IMR_OVRIE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SPDIFRX_IMR_SBLKIE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SPDIFRX_IMR_SYNCDIE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SPDIFRX_IMR_IFEIE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SPDIFRX_XIMR_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Bit definition for SPDIFRX_SR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SPDIFRX_SR_RXNE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SPDIFRX_SR_CSRNE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SPDIFRX_SR_PERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SPDIFRX_SR_OVR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SPDIFRX_SR_SBD BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SPDIFRX_SR_SYNCD BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SPDIFRX_SR_FERR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SPDIFRX_SR_SERR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SPDIFRX_SR_TERR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SPDIFRX_SR_WIDTH5_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Bit definition for SPDIFRX_IFCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SPDIFRX_IFCR_PERRCF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SPDIFRX_IFCR_OVRCF BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SPDIFRX_IFCR_SBDCF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SPDIFRX_IFCR_SYNCDCF BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SPDIFRX_XIFCR_MASK GENMASK(5, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SPDIFRX_DR0_DR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SPDIFRX_DR0_PE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SPDIFRX_DR0_V BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SPDIFRX_DR0_U BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SPDIFRX_DR0_C BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SPDIFRX_DR0_PT_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SPDIFRX_DR1_PE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SPDIFRX_DR1_V BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SPDIFRX_DR1_U BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SPDIFRX_DR1_C BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SPDIFRX_DR1_PT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SPDIFRX_DR1_DR_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SPDIFRX_DR1_DRNL1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SPDIFRX_DR1_DRNL2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Bit definition for SPDIFRX_CSR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SPDIFRX_CSR_USR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) >> SPDIFRX_CSR_USR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SPDIFRX_CSR_CS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) >> SPDIFRX_CSR_CS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SPDIFRX_CSR_SOB BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Bit definition for SPDIFRX_DIR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SPDIFRX_DIR_THI_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SPDIFRX_DIR_TLO_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SPDIFRX_SPDIFEN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SPDIFRX_SPDIFEN_SYNC 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SPDIFRX_SPDIFEN_ENABLE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Bit definition for SPDIFRX_VERR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SPDIFRX_VERR_MIN_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SPDIFRX_VERR_MAJ_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Bit definition for SPDIFRX_IDR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SPDIFRX_IDR_ID_MASK GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Bit definition for SPDIFRX_SIDR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SPDIFRX_SIDR_SID_MASK GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SPDIFRX_IPIDR_NUMBER 0x00130041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SPDIFRX_IN1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SPDIFRX_IN2 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SPDIFRX_IN3 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SPDIFRX_IN4 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SPDIFRX_IN5 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SPDIFRX_IN6 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SPDIFRX_IN7 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SPDIFRX_IN8 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SPDIFRX_NBTR_NONE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SPDIFRX_NBTR_3 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SPDIFRX_NBTR_15 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SPDIFRX_NBTR_63 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SPDIFRX_DRFMT_RIGHT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SPDIFRX_DRFMT_LEFT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SPDIFRX_DRFMT_PACKED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SPDIFRX_CS_BYTES_NB 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SPDIFRX_UB_BYTES_NB 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * CSR register is retrieved as a 32 bits word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * It contains 1 channel status byte and 2 user data bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * 2 S/PDIF frames are acquired to get all CS/UB bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * struct stm32_spdifrx_data - private data of SPDIFRX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * @pdev: device data pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * @base: mmio register base virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * @regmap: SPDIFRX register map pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * @regmap_conf: SPDIFRX register map configuration pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * @cs_completion: channel status retrieving completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * @kclk: kernel clock feeding the SPDIFRX clock generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * @dma_params: dma configuration data for rx channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @substream: PCM substream data pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @dmab: dma buffer info pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @ctrl_chan: dma channel for S/PDIF control bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @desc:dma async transaction descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @slave_config: dma slave channel runtime config pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @phys_addr: SPDIFRX registers physical base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @lock: synchronization enabling lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @irq_lock: prevent race condition with IRQ on stream state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @cs: channel status buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @ub: user data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @irq: SPDIFRX interrupt line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @refcount: keep count of opened DMA channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct stm32_spdifrx_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) const struct regmap_config *regmap_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct completion cs_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct clk *kclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct snd_dmaengine_dai_dma_data dma_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct snd_dma_buffer *dmab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct dma_chan *ctrl_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct dma_slave_config slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dma_addr_t phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) spinlock_t lock; /* Sync enabling lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) spinlock_t irq_lock; /* Prevent race condition on stream state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned char cs[SPDIFRX_CS_BYTES_NB];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned char ub[SPDIFRX_UB_BYTES_NB];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int refcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static void stm32_spdifrx_dma_complete(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct platform_device *pdev = spdifrx->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 *p_start = (u32 *)spdifrx->dmab->area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 *ptr = p_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u16 *ub_ptr = (short *)spdifrx->ub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) SPDIFRX_CR_CBDMAEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) (unsigned int)~SPDIFRX_CR_CBDMAEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (!spdifrx->dmab->area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) while (ptr <= p_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (*ptr & SPDIFRX_CSR_SOB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (ptr > p_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_err(&pdev->dev, "Start of S/PDIF block not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) while (i < SPDIFRX_CS_BYTES_NB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (ptr > p_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dev_err(&pdev->dev, "Failed to get channel status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) complete(&spdifrx->cs_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) spdifrx->dmab->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) SPDIFRX_CSR_BUF_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (!spdifrx->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) spdifrx->desc->callback = stm32_spdifrx_dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) spdifrx->desc->callback_param = spdifrx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) cookie = dmaengine_submit(spdifrx->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) err = dma_submit_error(cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dma_async_issue_pending(spdifrx->ctrl_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dmaengine_terminate_async(spdifrx->ctrl_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int cr, cr_mask, imr, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Enable IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) spin_lock_irqsave(&spdifrx->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) spdifrx->refcount++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * Start sync if SPDIFRX is still in idle state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * SPDIFRX reception enabled when sync done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_dbg(&spdifrx->pdev->dev, "start synchronization\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * SPDIFRX configuration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Wait for activity before starting sync process. This avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * to issue sync errors when spdif signal is missing on input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Preamble, CS, user, validity and parity error bits not copied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * to DR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) cr_mask = cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) cr |= SPDIFRX_CR_NBTRSET(SPDIFRX_NBTR_63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) cr_mask |= SPDIFRX_CR_NBTR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) cr_mask |= SPDIFRX_CR_SPDIFEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) cr_mask, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_err(&spdifrx->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) "Failed to start synchronization\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) spin_unlock_irqrestore(&spdifrx->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int cr, cr_mask, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) spin_lock_irqsave(&spdifrx->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (--spdifrx->refcount) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) spin_unlock_irqrestore(&spdifrx->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) SPDIFRX_XIMR_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* dummy read to clear CSRNE and RXNE in status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) spin_unlock_irqrestore(&spdifrx->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int stm32_spdifrx_dma_ctrl_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct stm32_spdifrx_data *spdifrx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (IS_ERR(spdifrx->ctrl_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (PTR_ERR(spdifrx->ctrl_chan) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dev_err(dev, "dma_request_slave_channel error %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) PTR_ERR(spdifrx->ctrl_chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return PTR_ERR(spdifrx->ctrl_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (!spdifrx->dmab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) spdifrx->dmab->dev.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) spdifrx->slave_config.direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) STM32_SPDIFRX_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) spdifrx->slave_config.dst_addr = spdifrx->dmab->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) spdifrx->slave_config.src_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = dmaengine_slave_config(spdifrx->ctrl_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) &spdifrx->slave_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dev_err(dev, "dmaengine_slave_config returned error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) spdifrx->ctrl_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static const char * const spdifrx_enum_input[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) "in0", "in1", "in2", "in3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* By default CS bits are retrieved from channel A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const char * const spdifrx_enum_cs_channel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) "A", "B"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static SOC_ENUM_SINGLE_DECL(ctrl_enum_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) spdifrx_enum_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) spdifrx_enum_cs_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = stm32_spdifrx_dma_ctrl_start(spdifrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ret = clk_prepare_enable(spdifrx->kclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ret = stm32_spdifrx_start_sync(spdifrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) msecs_to_jiffies(100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev_dbg(&spdifrx->pdev->dev, "Failed to get control data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) stm32_spdifrx_stop(spdifrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) stm32_spdifrx_dma_ctrl_stop(spdifrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) clk_disable_unprepare(spdifrx->kclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) stm32_spdifrx_get_ctrl_data(spdifrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ucontrol->value.iec958.status[0] = spdifrx->cs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ucontrol->value.iec958.status[1] = spdifrx->cs[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ucontrol->value.iec958.status[2] = spdifrx->cs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ucontrol->value.iec958.status[3] = spdifrx->cs[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ucontrol->value.iec958.status[4] = spdifrx->cs[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) stm32_spdifrx_get_ctrl_data(spdifrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ucontrol->value.iec958.status[0] = spdifrx->ub[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ucontrol->value.iec958.status[1] = spdifrx->ub[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ucontrol->value.iec958.status[2] = spdifrx->ub[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ucontrol->value.iec958.status[3] = spdifrx->ub[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ucontrol->value.iec958.status[4] = spdifrx->ub[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* Channel status control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .info = stm32_spdifrx_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .get = stm32_spdifrx_capture_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* User bits control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .name = "IEC958 User Bit Capture Default",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .access = SNDRV_CTL_ELEM_ACCESS_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .info = stm32_spdifrx_ub_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .get = stm32_spdif_user_bits_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) SOC_ENUM("SPDIFRX input", ctrl_enum_input),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ARRAY_SIZE(stm32_spdifrx_iec_ctrls));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return snd_soc_add_component_controls(cpu_dai->component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) stm32_spdifrx_ctrls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ARRAY_SIZE(stm32_spdifrx_ctrls));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) STM32_SPDIFRX_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) spdifrx->dma_params.maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return stm32_spdifrx_dai_register_ctrls(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) case STM32_SPDIFRX_CR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case STM32_SPDIFRX_IMR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) case STM32_SPDIFRX_SR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) case STM32_SPDIFRX_IFCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) case STM32_SPDIFRX_DR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) case STM32_SPDIFRX_CSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) case STM32_SPDIFRX_DIR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) case STM32_SPDIFRX_VERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) case STM32_SPDIFRX_IDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) case STM32_SPDIFRX_SIDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) case STM32_SPDIFRX_DR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) case STM32_SPDIFRX_CSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) case STM32_SPDIFRX_SR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) case STM32_SPDIFRX_DIR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) case STM32_SPDIFRX_CR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) case STM32_SPDIFRX_IMR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) case STM32_SPDIFRX_IFCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static const struct regmap_config stm32_h7_spdifrx_regmap_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .max_register = STM32_SPDIFRX_SIDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .readable_reg = stm32_spdifrx_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .volatile_reg = stm32_spdifrx_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .writeable_reg = stm32_spdifrx_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .num_reg_defaults_raw = STM32_SPDIFRX_SIDR / sizeof(u32) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static irqreturn_t stm32_spdifrx_isr(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct platform_device *pdev = spdifrx->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) unsigned int cr, mask, sr, imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) unsigned int flags, sync_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int err = 0, err_xrun = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) mask = imr & SPDIFRX_XIMR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* SERR, TERR, FERR IRQs are generated if IFEIE is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (mask & SPDIFRX_IMR_IFEIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) flags = sr & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (!flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) sr, imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Clear IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) SPDIFRX_XIFCR_MASK, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (flags & SPDIFRX_SR_PERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_dbg(&pdev->dev, "Parity error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) err_xrun = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (flags & SPDIFRX_SR_OVR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_dbg(&pdev->dev, "Overrun error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) err_xrun = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (flags & SPDIFRX_SR_SBD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dev_dbg(&pdev->dev, "Synchronization block detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (flags & SPDIFRX_SR_SYNCD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) dev_dbg(&pdev->dev, "Synchronization done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* Enable spdifrx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) SPDIFRX_CR_SPDIFEN_MASK, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (flags & SPDIFRX_SR_FERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dev_dbg(&pdev->dev, "Frame error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) err = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (flags & SPDIFRX_SR_SERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_dbg(&pdev->dev, "Synchronization error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) err = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (flags & SPDIFRX_SR_TERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dev_dbg(&pdev->dev, "Timeout error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) err = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) sync_state = FIELD_GET(SPDIFRX_CR_SPDIFEN_MASK, cr) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) SPDIFRX_SPDIFEN_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* SPDIFRX is in STATE_STOP. Disable SPDIFRX to clear errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) SPDIFRX_CR_SPDIFEN_MASK, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* If SPDIFRX was in STATE_SYNC, retry synchro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (sync_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) SPDIFRX_CR_SPDIFEN_MASK, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) spin_lock(&spdifrx->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (spdifrx->substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) snd_pcm_stop(spdifrx->substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) SNDRV_PCM_STATE_DISCONNECTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) spin_unlock(&spdifrx->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) spin_lock(&spdifrx->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (err_xrun && spdifrx->substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) snd_pcm_stop_xrun(spdifrx->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) spin_unlock(&spdifrx->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static int stm32_spdifrx_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) spin_lock_irqsave(&spdifrx->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) spdifrx->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ret = clk_prepare_enable(spdifrx->kclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) int data_size = params_width(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) int fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) switch (data_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) fmt = SPDIFRX_DRFMT_PACKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) fmt = SPDIFRX_DRFMT_LEFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev_err(&spdifrx->pdev->dev, "Unexpected data format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * Set buswidth to 4 bytes for all data formats.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * Packed format: transfer 2 x 2 bytes samples
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * Left format: transfer 1 x 3 bytes samples + 1 dummy byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) SPDIFRX_CR_DRFMT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) SPDIFRX_CR_DRFMTSET(fmt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ret = stm32_spdifrx_start_sync(spdifrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) stm32_spdifrx_stop(spdifrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) spin_lock_irqsave(&spdifrx->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) spdifrx->substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) clk_disable_unprepare(spdifrx->kclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .startup = stm32_spdifrx_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .hw_params = stm32_spdifrx_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .trigger = stm32_spdifrx_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .shutdown = stm32_spdifrx_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static struct snd_soc_dai_driver stm32_spdifrx_dai[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .probe = stm32_spdifrx_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .stream_name = "CPU-Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .formats = SNDRV_PCM_FMTBIT_S32_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .ops = &stm32_spdifrx_pcm_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .buffer_bytes_max = 8 * PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .period_bytes_min = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .period_bytes_max = 4 * PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .periods_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static const struct snd_soc_component_driver stm32_spdifrx_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .name = "stm32-spdifrx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .pcm_hardware = &stm32_spdifrx_pcm_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static const struct of_device_id stm32_spdifrx_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .compatible = "st,stm32h7-spdifrx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .data = &stm32_h7_spdifrx_regmap_conf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static int stm32_spdifrx_parse_of(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct stm32_spdifrx_data *spdifrx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) spdifrx->regmap_conf =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) (const struct regmap_config *)of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) spdifrx->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (IS_ERR(spdifrx->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return PTR_ERR(spdifrx->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) spdifrx->phys_addr = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (IS_ERR(spdifrx->kclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (PTR_ERR(spdifrx->kclk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) dev_err(&pdev->dev, "Could not get kclk: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) PTR_ERR(spdifrx->kclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return PTR_ERR(spdifrx->kclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) spdifrx->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (spdifrx->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return spdifrx->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static int stm32_spdifrx_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (spdifrx->ctrl_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) dma_release_channel(spdifrx->ctrl_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (spdifrx->dmab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) snd_dma_free_pages(spdifrx->dmab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) snd_dmaengine_pcm_unregister(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) snd_soc_unregister_component(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static int stm32_spdifrx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct stm32_spdifrx_data *spdifrx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) const struct snd_dmaengine_pcm_config *pcm_config = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u32 ver, idr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (!spdifrx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) spdifrx->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) init_completion(&spdifrx->cs_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) spin_lock_init(&spdifrx->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) spin_lock_init(&spdifrx->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) platform_set_drvdata(pdev, spdifrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ret = stm32_spdifrx_parse_of(pdev, spdifrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) spdifrx->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) spdifrx->regmap_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (IS_ERR(spdifrx->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (PTR_ERR(spdifrx->regmap) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) dev_err(&pdev->dev, "Regmap init error %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) PTR_ERR(spdifrx->regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return PTR_ERR(spdifrx->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) dev_name(&pdev->dev), spdifrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (IS_ERR(rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (PTR_ERR(rst) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) dev_err(&pdev->dev, "Reset controller error %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) PTR_ERR(rst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return PTR_ERR(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) reset_control_assert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) reset_control_deassert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) pcm_config = &stm32_spdifrx_pcm_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ret = snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) dev_err(&pdev->dev, "PCM DMA register error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) ret = snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) &stm32_spdifrx_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) stm32_spdifrx_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ARRAY_SIZE(stm32_spdifrx_dai));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) snd_dmaengine_pcm_unregister(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_IDR, &idr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (idr == SPDIFRX_IPIDR_NUMBER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_VERR, &ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) dev_dbg(&pdev->dev, "SPDIFRX version: %lu.%lu registered\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) FIELD_GET(SPDIFRX_VERR_MAJ_MASK, ver),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) FIELD_GET(SPDIFRX_VERR_MIN_MASK, ver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) stm32_spdifrx_remove(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static int stm32_spdifrx_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) regcache_cache_only(spdifrx->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) regcache_mark_dirty(spdifrx->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static int stm32_spdifrx_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) regcache_cache_only(spdifrx->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return regcache_sync(spdifrx->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static const struct dev_pm_ops stm32_spdifrx_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) SET_SYSTEM_SLEEP_PM_OPS(stm32_spdifrx_suspend, stm32_spdifrx_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static struct platform_driver stm32_spdifrx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .name = "st,stm32-spdifrx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .of_match_table = stm32_spdifrx_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .pm = &stm32_spdifrx_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .probe = stm32_spdifrx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .remove = stm32_spdifrx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) module_platform_driver(stm32_spdifrx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) MODULE_DESCRIPTION("STM32 Soc spdifrx Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) MODULE_ALIAS("platform:stm32-spdifrx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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