^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /******************** SAI Register Map **************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Global configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define STM_SAI_GCR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Sub-block A&B registers offsets, relative to A&B sub-block addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define STM_SAI_CR1_REGX 0x00 /* A offset: 0x04. B offset: 0x24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define STM_SAI_CR2_REGX 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define STM_SAI_FRCR_REGX 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define STM_SAI_SLOTR_REGX 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define STM_SAI_IMR_REGX 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define STM_SAI_SR_REGX 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STM_SAI_CLRFR_REGX 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STM_SAI_DR_REGX 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Sub-block A registers, relative to sub-block A address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define STM_SAI_PDMCR_REGX 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define STM_SAI_PDMLY_REGX 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Hardware configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define STM_SAI_HWCFGR 0x3F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define STM_SAI_VERR 0x3F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define STM_SAI_IDR 0x3F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define STM_SAI_SIDR 0x3FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /******************** Bit definition for SAI_GCR register *******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SAI_GCR_SYNCIN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SAI_GCR_SYNCIN_WDTH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SAI_GCR_SYNCIN_MASK GENMASK(1, SAI_GCR_SYNCIN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SAI_GCR_SYNCIN_MAX FIELD_GET(SAI_GCR_SYNCIN_MASK,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SAI_GCR_SYNCIN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SAI_GCR_SYNCOUT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SAI_GCR_SYNCOUT_MASK GENMASK(5, SAI_GCR_SYNCOUT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /******************* Bit definition for SAI_XCR1 register *******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SAI_XCR1_RX_TX_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SAI_XCR1_RX_TX BIT(SAI_XCR1_RX_TX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SAI_XCR1_SLAVE_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SAI_XCR1_SLAVE BIT(SAI_XCR1_SLAVE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SAI_XCR1_PRTCFG_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SAI_XCR1_PRTCFG_MASK GENMASK(3, SAI_XCR1_PRTCFG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SAI_XCR1_PRTCFG_SET(x) ((x) << SAI_XCR1_PRTCFG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SAI_XCR1_DS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SAI_XCR1_DS_MASK GENMASK(7, SAI_XCR1_DS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SAI_XCR1_DS_SET(x) ((x) << SAI_XCR1_DS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SAI_XCR1_LSBFIRST_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SAI_XCR1_LSBFIRST BIT(SAI_XCR1_LSBFIRST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SAI_XCR1_CKSTR_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SAI_XCR1_CKSTR BIT(SAI_XCR1_CKSTR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SAI_XCR1_SYNCEN_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SAI_XCR1_SYNCEN_MASK GENMASK(11, SAI_XCR1_SYNCEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SAI_XCR1_SYNCEN_SET(x) ((x) << SAI_XCR1_SYNCEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SAI_XCR1_MONO_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SAI_XCR1_MONO BIT(SAI_XCR1_MONO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SAI_XCR1_OUTDRIV_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SAI_XCR1_OUTDRIV BIT(SAI_XCR1_OUTDRIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SAI_XCR1_SAIEN_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SAI_XCR1_SAIEN BIT(SAI_XCR1_SAIEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SAI_XCR1_DMAEN_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SAI_XCR1_DMAEN BIT(SAI_XCR1_DMAEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SAI_XCR1_NODIV_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SAI_XCR1_NODIV BIT(SAI_XCR1_NODIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SAI_XCR1_MCKDIV_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SAI_XCR1_MCKDIV_WIDTH(x) (((x) == STM_SAI_STM32F4) ? 4 : 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SAI_XCR1_MCKDIV_MASK(x) GENMASK((SAI_XCR1_MCKDIV_SHIFT + (x) - 1),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SAI_XCR1_MCKDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SAI_XCR1_MCKDIV_SET(x) ((x) << SAI_XCR1_MCKDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SAI_XCR1_MCKDIV_MAX(x) ((1 << SAI_XCR1_MCKDIV_WIDTH(x)) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SAI_XCR1_OSR_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SAI_XCR1_OSR BIT(SAI_XCR1_OSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SAI_XCR1_MCKEN_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SAI_XCR1_MCKEN BIT(SAI_XCR1_MCKEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /******************* Bit definition for SAI_XCR2 register *******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SAI_XCR2_FTH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SAI_XCR2_FTH_MASK GENMASK(2, SAI_XCR2_FTH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SAI_XCR2_FTH_SET(x) ((x) << SAI_XCR2_FTH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SAI_XCR2_FFLUSH_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SAI_XCR2_FFLUSH BIT(SAI_XCR2_FFLUSH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SAI_XCR2_TRIS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SAI_XCR2_TRIS BIT(SAI_XCR2_TRIS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SAI_XCR2_MUTE_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SAI_XCR2_MUTE BIT(SAI_XCR2_MUTE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SAI_XCR2_MUTEVAL_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SAI_XCR2_MUTEVAL BIT(SAI_XCR2_MUTEVAL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SAI_XCR2_MUTECNT_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SAI_XCR2_MUTECNT_MASK GENMASK(12, SAI_XCR2_MUTECNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SAI_XCR2_MUTECNT_SET(x) ((x) << SAI_XCR2_MUTECNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SAI_XCR2_CPL_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SAI_XCR2_CPL BIT(SAI_XCR2_CPL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SAI_XCR2_COMP_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SAI_XCR2_COMP_MASK GENMASK(15, SAI_XCR2_COMP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SAI_XCR2_COMP_SET(x) ((x) << SAI_XCR2_COMP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /****************** Bit definition for SAI_XFRCR register *******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SAI_XFRCR_FRL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SAI_XFRCR_FRL_MASK GENMASK(7, SAI_XFRCR_FRL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SAI_XFRCR_FRL_SET(x) ((x) << SAI_XFRCR_FRL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SAI_XFRCR_FSALL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SAI_XFRCR_FSALL_MASK GENMASK(14, SAI_XFRCR_FSALL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SAI_XFRCR_FSALL_SET(x) ((x) << SAI_XFRCR_FSALL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SAI_XFRCR_FSDEF_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SAI_XFRCR_FSDEF BIT(SAI_XFRCR_FSDEF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SAI_XFRCR_FSPOL_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SAI_XFRCR_FSPOL BIT(SAI_XFRCR_FSPOL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SAI_XFRCR_FSOFF_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SAI_XFRCR_FSOFF BIT(SAI_XFRCR_FSOFF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /****************** Bit definition for SAI_XSLOTR register ******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SAI_XSLOTR_FBOFF_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SAI_XSLOTR_FBOFF_MASK GENMASK(4, SAI_XSLOTR_FBOFF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SAI_XSLOTR_FBOFF_SET(x) ((x) << SAI_XSLOTR_FBOFF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SAI_XSLOTR_SLOTSZ_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SAI_XSLOTR_SLOTSZ_MASK GENMASK(7, SAI_XSLOTR_SLOTSZ_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SAI_XSLOTR_SLOTSZ_SET(x) ((x) << SAI_XSLOTR_SLOTSZ_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SAI_XSLOTR_NBSLOT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SAI_XSLOTR_NBSLOT_MASK GENMASK(11, SAI_XSLOTR_NBSLOT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SAI_XSLOTR_NBSLOT_SET(x) ((x) << SAI_XSLOTR_NBSLOT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SAI_XSLOTR_SLOTEN_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SAI_XSLOTR_SLOTEN_WIDTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SAI_XSLOTR_SLOTEN_MASK GENMASK(31, SAI_XSLOTR_SLOTEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SAI_XSLOTR_SLOTEN_SET(x) ((x) << SAI_XSLOTR_SLOTEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /******************* Bit definition for SAI_XIMR register *******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SAI_XIMR_OVRUDRIE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SAI_XIMR_MUTEDETIE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SAI_XIMR_WCKCFGIE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SAI_XIMR_FREQIE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SAI_XIMR_CNRDYIE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SAI_XIMR_AFSDETIE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SAI_XIMR_LFSDETIE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SAI_XIMR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SAI_XIMR_MASK GENMASK(6, SAI_XIMR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /******************** Bit definition for SAI_XSR register *******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SAI_XSR_OVRUDR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SAI_XSR_MUTEDET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SAI_XSR_WCKCFG BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SAI_XSR_FREQ BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SAI_XSR_CNRDY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SAI_XSR_AFSDET BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SAI_XSR_LFSDET BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SAI_XSR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SAI_XSR_MASK GENMASK(6, SAI_XSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /****************** Bit definition for SAI_XCLRFR register ******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SAI_XCLRFR_COVRUDR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SAI_XCLRFR_CMUTEDET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SAI_XCLRFR_CWCKCFG BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SAI_XCLRFR_CFREQ BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SAI_XCLRFR_CCNRDY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SAI_XCLRFR_CAFSDET BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SAI_XCLRFR_CLFSDET BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SAI_XCLRFR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SAI_XCLRFR_MASK GENMASK(6, SAI_XCLRFR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /****************** Bit definition for SAI_PDMCR register ******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SAI_PDMCR_PDMEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SAI_PDMCR_MICNBR_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SAI_PDMCR_MICNBR_MASK GENMASK(5, SAI_PDMCR_MICNBR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SAI_PDMCR_MICNBR_SET(x) ((x) << SAI_PDMCR_MICNBR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SAI_PDMCR_CKEN1 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SAI_PDMCR_CKEN2 BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SAI_PDMCR_CKEN3 BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SAI_PDMCR_CKEN4 BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /****************** Bit definition for (SAI_PDMDLY register ****************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SAI_PDMDLY_1L_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SAI_PDMDLY_1L_MASK GENMASK(2, SAI_PDMDLY_1L_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SAI_PDMDLY_1L_WIDTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SAI_PDMDLY_1R_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SAI_PDMDLY_1R_MASK GENMASK(6, SAI_PDMDLY_1R_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SAI_PDMDLY_1R_WIDTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SAI_PDMDLY_2L_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SAI_PDMDLY_2L_MASK GENMASK(10, SAI_PDMDLY_2L_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SAI_PDMDLY_2L_WIDTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SAI_PDMDLY_2R_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SAI_PDMDLY_2R_MASK GENMASK(14, SAI_PDMDLY_2R_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SAI_PDMDLY_2R_WIDTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SAI_PDMDLY_3L_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SAI_PDMDLY_3L_MASK GENMASK(18, SAI_PDMDLY_3L_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SAI_PDMDLY_3L_WIDTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SAI_PDMDLY_3R_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SAI_PDMDLY_3R_MASK GENMASK(22, SAI_PDMDLY_3R_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SAI_PDMDLY_3R_WIDTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SAI_PDMDLY_4L_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SAI_PDMDLY_4L_MASK GENMASK(26, SAI_PDMDLY_4L_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SAI_PDMDLY_4L_WIDTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SAI_PDMDLY_4R_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SAI_PDMDLY_4R_MASK GENMASK(30, SAI_PDMDLY_4R_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SAI_PDMDLY_4R_WIDTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Registers below apply to SAI version 2.1 and more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Bit definition for SAI_HWCFGR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SAI_HWCFGR_FIFO_SIZE GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SAI_HWCFGR_SPDIF_PDM GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SAI_HWCFGR_REGOUT GENMASK(19, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Bit definition for SAI_VERR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SAI_VERR_MIN_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SAI_VERR_MAJ_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Bit definition for SAI_IDR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SAI_IDR_ID_MASK GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Bit definition for SAI_SIDR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SAI_SIDR_ID_MASK GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SAI_IPIDR_NUMBER 0x00130031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* SAI version numbers are 1.x for F4. Major version number set to 1 for F4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define STM_SAI_STM32F4 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Dummy version number for H7 socs and next */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define STM_SAI_STM32H7 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define STM_SAI_IS_F4(ip) ((ip)->conf.version == STM_SAI_STM32F4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define STM_SAI_HAS_SPDIF_PDM(ip)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ((ip)->pdata->conf.has_spdif_pdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) enum stm32_sai_syncout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) STM_SAI_SYNC_OUT_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) STM_SAI_SYNC_OUT_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) STM_SAI_SYNC_OUT_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * struct stm32_sai_conf - SAI configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * @version: SAI version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * @fifo_size: SAI fifo size as words number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * @has_spdif_pdm: SAI S/PDIF and PDM features support flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct stm32_sai_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) bool has_spdif_pdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * struct stm32_sai_data - private data of SAI instance driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * @pdev: device data pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * @base: common register bank virtual base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * @pclk: SAI bus clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * @clk_x8k: SAI parent clock for sampling frequencies multiple of 8kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * @clk_x11k: SAI parent clock for sampling frequencies multiple of 11kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * @conf: SAI hardware capabitilites
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * @irq: SAI interrupt line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * @set_sync: pointer to synchro mode configuration callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * @gcr: SAI Global Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct stm32_sai_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct clk *clk_x8k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct clk *clk_x11k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct stm32_sai_conf conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int (*set_sync)(struct stm32_sai_data *sai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct device_node *np_provider, int synco, int synci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 gcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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