Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "stm32_sai.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static const struct stm32_sai_conf stm32_sai_conf_f4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	.version = STM_SAI_STM32F4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	.fifo_size = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	.has_spdif_pdm = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * Default settings for stm32 H7 socs and next.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * These default settings will be overridden if the soc provides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * support of hardware configuration registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static const struct stm32_sai_conf stm32_sai_conf_h7 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	.version = STM_SAI_STM32H7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	.fifo_size = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	.has_spdif_pdm = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static const struct of_device_id stm32_sai_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	{ .compatible = "st,stm32f4-sai", .data = (void *)&stm32_sai_conf_f4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	{ .compatible = "st,stm32h7-sai", .data = (void *)&stm32_sai_conf_h7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static int stm32_sai_pclk_disable(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct stm32_sai_data *sai = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	clk_disable_unprepare(sai->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static int stm32_sai_pclk_enable(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct stm32_sai_data *sai = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	ret = clk_prepare_enable(sai->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		dev_err(&sai->pdev->dev, "failed to enable clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static int stm32_sai_sync_conf_client(struct stm32_sai_data *sai, int synci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	/* Enable peripheral clock to allow GCR register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	ret = stm32_sai_pclk_enable(&sai->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	writel_relaxed(FIELD_PREP(SAI_GCR_SYNCIN_MASK, (synci - 1)), sai->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	stm32_sai_pclk_disable(&sai->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static int stm32_sai_sync_conf_provider(struct stm32_sai_data *sai, int synco)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u32 prev_synco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	/* Enable peripheral clock to allow GCR register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	ret = stm32_sai_pclk_enable(&sai->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	dev_dbg(&sai->pdev->dev, "Set %pOFn%s as synchro provider\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		sai->pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	prev_synco = FIELD_GET(SAI_GCR_SYNCOUT_MASK, readl_relaxed(sai->base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (prev_synco != STM_SAI_SYNC_OUT_NONE && synco != prev_synco) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		dev_err(&sai->pdev->dev, "%pOFn%s already set as sync provider\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			sai->pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			prev_synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		stm32_sai_pclk_disable(&sai->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	writel_relaxed(FIELD_PREP(SAI_GCR_SYNCOUT_MASK, synco), sai->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	stm32_sai_pclk_disable(&sai->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int stm32_sai_set_sync(struct stm32_sai_data *sai_client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			      struct device_node *np_provider,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			      int synco, int synci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct platform_device *pdev = of_find_device_by_node(np_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct stm32_sai_data *sai_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (!pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		dev_err(&sai_client->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			"Device not found for node %pOFn\n", np_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		of_node_put(np_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	sai_provider = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (!sai_provider) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		dev_err(&sai_client->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			"SAI sync provider data not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	/* Configure sync client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	ret = stm32_sai_sync_conf_client(sai_client, synci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	/* Configure sync provider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	ret = stm32_sai_sync_conf_provider(sai_provider, synco);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	put_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	of_node_put(np_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int stm32_sai_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct stm32_sai_data *sai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (!sai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	sai->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (IS_ERR(sai->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		return PTR_ERR(sai->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	of_id = of_match_device(stm32_sai_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		memcpy(&sai->conf, (const struct stm32_sai_conf *)of_id->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		       sizeof(struct stm32_sai_conf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (!STM_SAI_IS_F4(sai)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		sai->pclk = devm_clk_get(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		if (IS_ERR(sai->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			if (PTR_ERR(sai->pclk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 				dev_err(&pdev->dev, "missing bus clock pclk: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 					PTR_ERR(sai->pclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			return PTR_ERR(sai->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	sai->clk_x8k = devm_clk_get(&pdev->dev, "x8k");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (IS_ERR(sai->clk_x8k)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		if (PTR_ERR(sai->clk_x8k) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			dev_err(&pdev->dev, "missing x8k parent clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				PTR_ERR(sai->clk_x8k));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		return PTR_ERR(sai->clk_x8k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	sai->clk_x11k = devm_clk_get(&pdev->dev, "x11k");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (IS_ERR(sai->clk_x11k)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		if (PTR_ERR(sai->clk_x11k) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			dev_err(&pdev->dev, "missing x11k parent clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 				PTR_ERR(sai->clk_x11k));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return PTR_ERR(sai->clk_x11k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* init irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	sai->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (sai->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		return sai->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	/* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (IS_ERR(rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		if (PTR_ERR(rst) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			dev_err(&pdev->dev, "Reset controller error %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				PTR_ERR(rst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		return PTR_ERR(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	reset_control_assert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	reset_control_deassert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	/* Enable peripheral clock to allow register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	ret = clk_prepare_enable(sai->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	val = FIELD_GET(SAI_IDR_ID_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			readl_relaxed(sai->base + STM_SAI_IDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (val == SAI_IPIDR_NUMBER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		val = readl_relaxed(sai->base + STM_SAI_HWCFGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		sai->conf.fifo_size = FIELD_GET(SAI_HWCFGR_FIFO_SIZE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		sai->conf.has_spdif_pdm = !!FIELD_GET(SAI_HWCFGR_SPDIF_PDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 						      val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		val = readl_relaxed(sai->base + STM_SAI_VERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		sai->conf.version = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		dev_dbg(&pdev->dev, "SAI version: %lu.%lu registered\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			FIELD_GET(SAI_VERR_MAJ_MASK, val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			FIELD_GET(SAI_VERR_MIN_MASK, val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	clk_disable_unprepare(sai->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	sai->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	sai->set_sync = &stm32_sai_set_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	platform_set_drvdata(pdev, sai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	return devm_of_platform_populate(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  * When pins are shared by two sai sub instances, pins have to be defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  * in sai parent node. In this case, pins state is not managed by alsa fw.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  * These pins are managed in suspend/resume callbacks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int stm32_sai_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	struct stm32_sai_data *sai = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	ret = stm32_sai_pclk_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	sai->gcr = readl_relaxed(sai->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	stm32_sai_pclk_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	return pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int stm32_sai_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	struct stm32_sai_data *sai = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	ret = stm32_sai_pclk_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	writel_relaxed(sai->gcr, sai->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	stm32_sai_pclk_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	return pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct dev_pm_ops stm32_sai_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_suspend, stm32_sai_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MODULE_DEVICE_TABLE(of, stm32_sai_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static struct platform_driver stm32_sai_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.name = "st,stm32-sai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		.of_match_table = stm32_sai_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		.pm = &stm32_sai_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.probe = stm32_sai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) module_platform_driver(stm32_sai_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_DESCRIPTION("STM32 Soc SAI Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_ALIAS("platform:st,stm32-sai");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_LICENSE("GPL v2");