^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * STM32 ALSA SoC Digital Audio Interface (I2S) driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define STM32_I2S_CR1_REG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STM32_I2S_CFG1_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STM32_I2S_CFG2_REG 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STM32_I2S_IER_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define STM32_I2S_SR_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define STM32_I2S_IFCR_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define STM32_I2S_TXDR_REG 0X20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define STM32_I2S_RXDR_REG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define STM32_I2S_CGFR_REG 0X50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define STM32_I2S_HWCFGR_REG 0x3F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define STM32_I2S_VERR_REG 0x3F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define STM32_I2S_IPIDR_REG 0x3F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define STM32_I2S_SIDR_REG 0x3FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Bit definition for SPI2S_CR1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define I2S_CR1_SPE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define I2S_CR1_CSTART BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define I2S_CR1_CSUSP BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I2S_CR1_HDDIR BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I2S_CR1_SSI BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I2S_CR1_CRC33_17 BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I2S_CR1_RCRCI BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I2S_CR1_TCRCI BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Bit definition for SPI_CFG2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define I2S_CFG2_IOSWP_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define I2S_CFG2_IOSWP BIT(I2S_CFG2_IOSWP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define I2S_CFG2_LSBFRST BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define I2S_CFG2_AFCNTR BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Bit definition for SPI_CFG1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define I2S_CFG1_FTHVL_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define I2S_CFG1_FTHVL_MASK GENMASK(8, I2S_CFG1_FTHVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define I2S_CFG1_FTHVL_SET(x) ((x) << I2S_CFG1_FTHVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define I2S_CFG1_TXDMAEN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define I2S_CFG1_RXDMAEN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Bit definition for SPI2S_IER register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2S_IER_RXPIE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I2S_IER_TXPIE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I2S_IER_DPXPIE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define I2S_IER_EOTIE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define I2S_IER_TXTFIE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define I2S_IER_UDRIE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define I2S_IER_OVRIE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define I2S_IER_CRCEIE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define I2S_IER_TIFREIE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define I2S_IER_MODFIE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define I2S_IER_TSERFIE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Bit definition for SPI2S_SR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define I2S_SR_RXP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define I2S_SR_TXP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define I2S_SR_DPXP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define I2S_SR_EOT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define I2S_SR_TXTF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define I2S_SR_UDR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define I2S_SR_OVR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define I2S_SR_CRCERR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define I2S_SR_TIFRE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define I2S_SR_MODF BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define I2S_SR_TSERF BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define I2S_SR_SUSP BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define I2S_SR_TXC BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define I2S_SR_RXPLVL GENMASK(14, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define I2S_SR_RXWNE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define I2S_SR_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Bit definition for SPI_IFCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define I2S_IFCR_EOTC BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define I2S_IFCR_TXTFC BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define I2S_IFCR_UDRC BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define I2S_IFCR_OVRC BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define I2S_IFCR_CRCEC BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define I2S_IFCR_TIFREC BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define I2S_IFCR_MODFC BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define I2S_IFCR_TSERFC BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define I2S_IFCR_SUSPC BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define I2S_IFCR_MASK GENMASK(11, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Bit definition for SPI_I2SCGFR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define I2S_CGFR_I2SMOD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define I2S_CGFR_I2SCFG_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define I2S_CGFR_I2SCFG_MASK GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define I2S_CGFR_I2SCFG_SET(x) ((x) << I2S_CGFR_I2SCFG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define I2S_CGFR_I2SSTD_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define I2S_CGFR_I2SSTD_MASK GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define I2S_CGFR_I2SSTD_SET(x) ((x) << I2S_CGFR_I2SSTD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define I2S_CGFR_PCMSYNC BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define I2S_CGFR_DATLEN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define I2S_CGFR_DATLEN_MASK GENMASK(9, I2S_CGFR_DATLEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define I2S_CGFR_DATLEN_SET(x) ((x) << I2S_CGFR_DATLEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define I2S_CGFR_CHLEN_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define I2S_CGFR_CHLEN BIT(I2S_CGFR_CHLEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define I2S_CGFR_CKPOL BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define I2S_CGFR_FIXCH BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define I2S_CGFR_WSINV BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define I2S_CGFR_DATFMT BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define I2S_CGFR_I2SDIV_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define I2S_CGFR_I2SDIV_BIT_H 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define I2S_CGFR_I2SDIV_MASK GENMASK(I2S_CGFR_I2SDIV_BIT_H,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) I2S_CGFR_I2SDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define I2S_CGFR_I2SDIV_SET(x) ((x) << I2S_CGFR_I2SDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) I2S_CGFR_I2SDIV_SHIFT)) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define I2S_CGFR_ODD_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define I2S_CGFR_ODD BIT(I2S_CGFR_ODD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define I2S_CGFR_MCKOE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Registers below apply to I2S version 1.1 and more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Bit definition for SPI_HWCFGR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define I2S_HWCFGR_I2S_SUPPORT_MASK GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Bit definition for SPI_VERR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define I2S_VERR_MIN_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define I2S_VERR_MAJ_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Bit definition for SPI_IPIDR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define I2S_IPIDR_ID_MASK GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Bit definition for SPI_SIDR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define I2S_SIDR_ID_MASK GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define I2S_IPIDR_NUMBER 0x00130022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) enum i2s_master_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) I2S_MS_NOT_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) I2S_MS_MASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) I2S_MS_SLAVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) enum i2s_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) I2S_I2SMOD_TX_SLAVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) I2S_I2SMOD_RX_SLAVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) I2S_I2SMOD_TX_MASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) I2S_I2SMOD_RX_MASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) I2S_I2SMOD_FD_SLAVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) I2S_I2SMOD_FD_MASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) enum i2s_fifo_th {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) I2S_FIFO_TH_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) I2S_FIFO_TH_ONE_QUARTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) I2S_FIFO_TH_HALF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) I2S_FIFO_TH_THREE_QUARTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) I2S_FIFO_TH_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) enum i2s_std {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) I2S_STD_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) I2S_STD_LEFT_J,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) I2S_STD_RIGHT_J,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) I2S_STD_DSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) enum i2s_datlen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) I2S_I2SMOD_DATLEN_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) I2S_I2SMOD_DATLEN_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) I2S_I2SMOD_DATLEN_32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define STM32_I2S_FIFO_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * struct stm32_i2s_data - private data of I2S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * @regmap_conf: I2S register map configuration pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * @regmap: I2S register map pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * @pdev: device data pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * @dai_drv: DAI driver pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * @dma_data_tx: dma configuration data for tx channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @dma_data_rx: dma configuration data for tx channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * @substream: PCM substream data pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * @i2sclk: kernel clock feeding the I2S clock generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * @pclk: peripheral clock driving bus interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * @base: mmio register base virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * @phys_addr: I2S registers physical base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * @lock_fd: lock to manage race conditions in full duplex mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @irq_lock: prevent race condition with IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @mclk_rate: master clock frequency (Hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @fmt: DAI protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @refcount: keep count of opened streams on I2S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @ms_flg: master mode flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct stm32_i2s_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) const struct regmap_config *regmap_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct snd_soc_dai_driver *dai_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct snd_dmaengine_dai_dma_data dma_data_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct snd_dmaengine_dai_dma_data dma_data_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct clk *i2sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct clk *x8kclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct clk *x11kclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dma_addr_t phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) spinlock_t lock_fd; /* Manage race conditions for full duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) spinlock_t irq_lock; /* used to prevent race condition with IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned int mclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned int fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int refcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int ms_flg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static irqreturn_t stm32_i2s_isr(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct platform_device *pdev = i2s->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 sr, ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) flags = sr & ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (!flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) sr, ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) I2S_IFCR_MASK, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (flags & I2S_SR_OVR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev_dbg(&pdev->dev, "Overrun\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) err = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (flags & I2S_SR_UDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dev_dbg(&pdev->dev, "Underrun\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) err = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (flags & I2S_SR_TIFRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_dbg(&pdev->dev, "Frame error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) spin_lock(&i2s->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (err && i2s->substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) snd_pcm_stop_xrun(i2s->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) spin_unlock(&i2s->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case STM32_I2S_CR1_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) case STM32_I2S_CFG1_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case STM32_I2S_CFG2_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case STM32_I2S_IER_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case STM32_I2S_SR_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) case STM32_I2S_RXDR_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case STM32_I2S_CGFR_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case STM32_I2S_HWCFGR_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case STM32_I2S_VERR_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case STM32_I2S_IPIDR_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case STM32_I2S_SIDR_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) case STM32_I2S_SR_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case STM32_I2S_RXDR_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case STM32_I2S_CR1_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) case STM32_I2S_CFG1_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case STM32_I2S_CFG2_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case STM32_I2S_IER_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case STM32_I2S_IFCR_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) case STM32_I2S_TXDR_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case STM32_I2S_CGFR_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 cgfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 cgfr_mask = I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * winv = 0 : default behavior (high/low) for all standards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * ckpol = 0 for all standards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case SND_SOC_DAIFMT_MSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case SND_SOC_DAIFMT_LSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) fmt & SND_SOC_DAIFMT_FORMAT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* DAI clock strobing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) cgfr |= I2S_CGFR_CKPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) cgfr |= I2S_CGFR_WSINV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) cgfr |= I2S_CGFR_CKPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) cgfr |= I2S_CGFR_WSINV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) fmt & SND_SOC_DAIFMT_INV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* DAI clock master masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) i2s->ms_flg = I2S_MS_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) i2s->ms_flg = I2S_MS_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) fmt & SND_SOC_DAIFMT_MASTER_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) i2s->fmt = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) cgfr_mask, cgfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int clk_id, unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz\n", freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if ((dir == SND_SOC_CLOCK_OUT) && STM32_I2S_IS_MASTER(i2s)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) i2s->mclk_rate = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Enable master clock if master mode and mclk-fs are set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned long i2s_clock_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) unsigned int tmp, div, real_div, nb_bits, frame_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned int rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u32 cgfr, cgfr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) bool odd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (!(rate % 11025))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) clk_set_parent(i2s->i2sclk, i2s->x11kclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) clk_set_parent(i2s->i2sclk, i2s->x8kclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) i2s_clock_rate = clk_get_rate(i2s->i2sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * mckl = mclk_ratio x ws
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * i2s mode : mclk_ratio = 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * dsp mode : mclk_ratio = 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * mclk on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * i2s mode : div = i2s_clk / (mclk_ratio * ws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * dsp mode : div = i2s_clk / (mclk_ratio * ws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * mclk off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * i2s mode : div = i2s_clk / (nb_bits x ws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * dsp mode : div = i2s_clk / (nb_bits x ws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (i2s->mclk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, i2s->mclk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) frame_len = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) SND_SOC_DAIFMT_DSP_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) frame_len = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* master clock not enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) nb_bits = frame_len * ((cgfr & I2S_CGFR_CHLEN) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, (nb_bits * rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Check the parity of the divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) odd = tmp & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Compute the div prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) div = tmp >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) cgfr = I2S_CGFR_I2SDIV_SET(div) | (odd << I2S_CGFR_ODD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) real_div = ((2 * div) + odd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev_dbg(cpu_dai->dev, "I2S clk: %ld, SCLK: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) i2s_clock_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_dbg(cpu_dai->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) div, odd, real_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (((div == 1) && odd) || (div > I2S_CGFR_I2SDIV_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_err(cpu_dai->dev, "Wrong divider setting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (!div && !odd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_warn(cpu_dai->dev, "real divider forced to 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) cgfr_mask, cgfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Set bitclock and frameclock to their inactive state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) int format = params_width(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u32 cfgr, cfgr_mask, cfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned int fthlv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) switch (format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) I2S_CGFR_CHLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev_err(cpu_dai->dev, "Unexpected format %d", format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (STM32_I2S_IS_SLAVE(i2s)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* As data length is either 16 or 32 bits, fixch always set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) cfgr |= I2S_CGFR_FIXCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) cfgr_mask |= I2S_CGFR_FIXCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) cfgr_mask |= I2S_CGFR_I2SCFG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) cfgr_mask, cfgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) I2S_CFG1_FTHVL_MASK, cfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int stm32_i2s_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) spin_lock_irqsave(&i2s->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) i2s->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) spin_unlock_irqrestore(&i2s->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) snd_pcm_hw_constraint_single(substream->runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) SNDRV_PCM_HW_PARAM_CHANNELS, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ret = clk_prepare_enable(i2s->i2sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) I2S_IFCR_MASK, I2S_IFCR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = stm32_i2s_configure(cpu_dai, params, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (STM32_I2S_IS_MASTER(i2s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = stm32_i2s_configure_clock(cpu_dai, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u32 cfg1_mask, ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Enable i2s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dev_dbg(cpu_dai->dev, "start I2S %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) playback_flg ? "playback" : "capture");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) cfg1_mask, cfg1_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) I2S_CR1_SPE, I2S_CR1_SPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) I2S_CR1_CSTART, I2S_CR1_CSTART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) I2S_IFCR_MASK, I2S_IFCR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) spin_lock(&i2s->lock_fd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) i2s->refcount++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (playback_flg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ier = I2S_IER_UDRIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ier = I2S_IER_OVRIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* dummy write to gate bus clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) regmap_write(i2s->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) STM32_I2S_TXDR_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) spin_unlock(&i2s->lock_fd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (STM32_I2S_IS_SLAVE(i2s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ier |= I2S_IER_TIFREIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dev_dbg(cpu_dai->dev, "stop I2S %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) playback_flg ? "playback" : "capture");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (playback_flg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) I2S_IER_UDRIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) (unsigned int)~I2S_IER_UDRIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) I2S_IER_OVRIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) (unsigned int)~I2S_IER_OVRIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) spin_lock(&i2s->lock_fd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) i2s->refcount--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (i2s->refcount) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) spin_unlock(&i2s->lock_fd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) I2S_CR1_SPE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) spin_unlock(&i2s->lock_fd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) spin_unlock(&i2s->lock_fd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) cfg1_mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) I2S_CGFR_MCKOE, (unsigned int)~I2S_CGFR_MCKOE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) clk_disable_unprepare(i2s->i2sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) spin_lock_irqsave(&i2s->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) i2s->substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) spin_unlock_irqrestore(&i2s->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* Buswidth will be set by framework */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dma_data_tx->maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dma_data_rx->maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static const struct regmap_config stm32_h7_i2s_regmap_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .max_register = STM32_I2S_SIDR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .readable_reg = stm32_i2s_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .volatile_reg = stm32_i2s_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .writeable_reg = stm32_i2s_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .num_reg_defaults_raw = STM32_I2S_SIDR_REG / sizeof(u32) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .set_sysclk = stm32_i2s_set_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .set_fmt = stm32_i2s_set_dai_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .startup = stm32_i2s_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .hw_params = stm32_i2s_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .trigger = stm32_i2s_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .shutdown = stm32_i2s_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const struct snd_pcm_hardware stm32_i2s_pcm_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .buffer_bytes_max = 8 * PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .period_bytes_min = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .period_bytes_max = 4 * PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .periods_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .pcm_hardware = &stm32_i2s_pcm_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .prealloc_buffer_size = PAGE_SIZE * 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static const struct snd_soc_component_driver stm32_i2s_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .name = "stm32-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) char *stream_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) stream->stream_name = stream_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) stream->channels_min = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) stream->channels_max = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) stream->rates = SNDRV_PCM_RATE_8000_192000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) stream->formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) SNDRV_PCM_FMTBIT_S32_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static int stm32_i2s_dais_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct stm32_i2s_data *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct snd_soc_dai_driver *dai_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (!dai_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) dai_ptr->probe = stm32_i2s_dai_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dai_ptr->ops = &stm32_i2s_pcm_dai_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) dai_ptr->id = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) stm32_i2s_dai_init(&dai_ptr->playback, "playback");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) stm32_i2s_dai_init(&dai_ptr->capture, "capture");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) i2s->dai_drv = dai_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static const struct of_device_id stm32_i2s_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .compatible = "st,stm32h7-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .data = &stm32_h7_i2s_regmap_conf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static int stm32_i2s_parse_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct stm32_i2s_data *i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) of_id = of_match_device(stm32_i2s_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) i2s->regmap_conf = (const struct regmap_config *)of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) i2s->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (IS_ERR(i2s->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return PTR_ERR(i2s->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) i2s->phys_addr = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* Get clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) i2s->pclk = devm_clk_get(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (IS_ERR(i2s->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (PTR_ERR(i2s->pclk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dev_err(&pdev->dev, "Could not get pclk: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) PTR_ERR(i2s->pclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return PTR_ERR(i2s->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (IS_ERR(i2s->i2sclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (PTR_ERR(i2s->i2sclk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) dev_err(&pdev->dev, "Could not get i2sclk: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) PTR_ERR(i2s->i2sclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return PTR_ERR(i2s->i2sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (IS_ERR(i2s->x8kclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (PTR_ERR(i2s->x8kclk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dev_err(&pdev->dev, "Could not get x8k parent clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) PTR_ERR(i2s->x8kclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return PTR_ERR(i2s->x8kclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (IS_ERR(i2s->x11kclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (PTR_ERR(i2s->x11kclk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dev_err(&pdev->dev, "Could not get x11k parent clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) PTR_ERR(i2s->x11kclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return PTR_ERR(i2s->x11kclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* Get irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) dev_name(&pdev->dev), i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) dev_err(&pdev->dev, "irq request returned %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (IS_ERR(rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (PTR_ERR(rst) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) dev_err(&pdev->dev, "Reset controller error %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) PTR_ERR(rst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return PTR_ERR(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) reset_control_assert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) reset_control_deassert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static int stm32_i2s_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) snd_dmaengine_pcm_unregister(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) snd_soc_unregister_component(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static int stm32_i2s_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct stm32_i2s_data *i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (!i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) ret = stm32_i2s_parse_dt(pdev, i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) i2s->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) i2s->ms_flg = I2S_MS_NOT_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) spin_lock_init(&i2s->lock_fd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) spin_lock_init(&i2s->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) platform_set_drvdata(pdev, i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ret = stm32_i2s_dais_init(pdev, i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) i2s->base, i2s->regmap_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (IS_ERR(i2s->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (PTR_ERR(i2s->regmap) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) dev_err(&pdev->dev, "Regmap init error %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) PTR_ERR(i2s->regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return PTR_ERR(i2s->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ret = snd_dmaengine_pcm_register(&pdev->dev, &stm32_i2s_pcm_config, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) dev_err(&pdev->dev, "PCM DMA register error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ret = snd_soc_register_component(&pdev->dev, &stm32_i2s_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) i2s->dai_drv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) snd_dmaengine_pcm_unregister(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* Set SPI/I2S in i2s mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (val == I2S_IPIDR_NUMBER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (!FIELD_GET(I2S_HWCFGR_I2S_SUPPORT_MASK, val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) "Device does not support i2s mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ret = -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dev_dbg(&pdev->dev, "I2S version: %lu.%lu registered\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) FIELD_GET(I2S_VERR_MAJ_MASK, val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) FIELD_GET(I2S_VERR_MIN_MASK, val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) stm32_i2s_remove(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) MODULE_DEVICE_TABLE(of, stm32_i2s_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static int stm32_i2s_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) regcache_cache_only(i2s->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) regcache_mark_dirty(i2s->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static int stm32_i2s_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) regcache_cache_only(i2s->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) return regcache_sync(i2s->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static const struct dev_pm_ops stm32_i2s_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) SET_SYSTEM_SLEEP_PM_OPS(stm32_i2s_suspend, stm32_i2s_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static struct platform_driver stm32_i2s_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .name = "st,stm32-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .of_match_table = stm32_i2s_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .pm = &stm32_i2s_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .probe = stm32_i2s_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .remove = stm32_i2s_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) module_platform_driver(stm32_i2s_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) MODULE_DESCRIPTION("STM32 Soc i2s Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) MODULE_ALIAS("platform:stm32-i2s");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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