Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * ALSA SoC SPDIF Out Audio Layer for spear processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Vipin Kumar <vipin.kumar@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <sound/spear_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <sound/spear_spdif.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "spdif_out_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include "spear_pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) struct spdif_out_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	u32 core_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u32 mute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) struct spdif_out_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct spear_dma_data dma_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct spdif_out_params saved_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u32 running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct snd_dmaengine_dai_dma_data dma_params_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct snd_dmaengine_pcm_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static void spdif_out_configure(struct spdif_out_dev *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	writel(SPDIF_OUT_RESET, host->io_base + SPDIF_OUT_SOFT_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	writel(readl(host->io_base + SPDIF_OUT_SOFT_RST) & ~SPDIF_OUT_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			host->io_base + SPDIF_OUT_SOFT_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	writel(SPDIF_OUT_FDMA_TRIG_16 | SPDIF_OUT_MEMFMT_16_16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			SPDIF_OUT_VALID_HW | SPDIF_OUT_USER_HW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			SPDIF_OUT_CHNLSTA_HW | SPDIF_OUT_PARITY_HW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			host->io_base + SPDIF_OUT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	writel(0x7F, host->io_base + SPDIF_OUT_INT_STA_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	writel(0x7F, host->io_base + SPDIF_OUT_INT_EN_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static int spdif_out_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct spdif_out_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	ret = clk_enable(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	host->running = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	spdif_out_configure(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static void spdif_out_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct spdif_out_dev *host = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	clk_disable(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	host->running = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static void spdif_out_clock(struct spdif_out_dev *host, u32 core_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	u32 divider, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	clk_set_rate(host->clk, core_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	divider = DIV_ROUND_CLOSEST(clk_get_rate(host->clk), (rate * 128));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	ctrl = readl(host->io_base + SPDIF_OUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	ctrl &= ~SPDIF_DIVIDER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	ctrl |= (divider << SPDIF_DIVIDER_SHIFT) & SPDIF_DIVIDER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	writel(ctrl, host->io_base + SPDIF_OUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int spdif_out_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct spdif_out_dev *host = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	u32 rate, core_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	case 64000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		 * The clock is multiplied by 10 to bring it to feasible range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		 * of frequencies for sscg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		core_freq = 64000 * 128 * 10;	/* 81.92 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	case 5512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	case 11025:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	case 22050:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	case 176400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		core_freq = 176400 * 128;	/* 22.5792 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		core_freq = 192000 * 128;	/* 24.576 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	spdif_out_clock(host, core_freq, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	host->saved_params.core_freq = core_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	host->saved_params.rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int spdif_out_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct spdif_out_dev *host = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			ctrl = readl(host->io_base + SPDIF_OUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			ctrl &= ~SPDIF_OPMODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			if (!host->saved_params.mute)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				ctrl |= SPDIF_OPMODE_AUD_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 					SPDIF_STATE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 				ctrl |= SPDIF_OPMODE_MUTE_PCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			writel(ctrl, host->io_base + SPDIF_OUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		ctrl = readl(host->io_base + SPDIF_OUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		ctrl &= ~SPDIF_OPMODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		ctrl |= SPDIF_OPMODE_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		writel(ctrl, host->io_base + SPDIF_OUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int spdif_mute(struct snd_soc_dai *dai, int mute, int direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct spdif_out_dev *host = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	host->saved_params.mute = mute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	val = readl(host->io_base + SPDIF_OUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	val &= ~SPDIF_OPMODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (mute)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		val |= SPDIF_OPMODE_MUTE_PCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		if (host->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			val |= SPDIF_OPMODE_AUD_DATA | SPDIF_STATE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			val |= SPDIF_OPMODE_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	writel(val, host->io_base + SPDIF_OUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int spdif_mute_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	struct spdif_out_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	ucontrol->value.integer.value[0] = host->saved_params.mute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int spdif_mute_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct spdif_out_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (host->saved_params.mute == ucontrol->value.integer.value[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	spdif_mute(cpu_dai, ucontrol->value.integer.value[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		   SNDRV_PCM_STREAM_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const struct snd_kcontrol_new spdif_out_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	SOC_SINGLE_BOOL_EXT("IEC958 Playback Switch", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			spdif_mute_get, spdif_mute_put),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int spdif_soc_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct spdif_out_dev *host = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	host->dma_params_tx.filter_data = &host->dma_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	dai->playback_dma_data = &host->dma_params_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	return snd_soc_add_dai_controls(dai, spdif_out_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 				ARRAY_SIZE(spdif_out_controls));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const struct snd_soc_dai_ops spdif_out_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.mute_stream	= spdif_mute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	.startup	= spdif_out_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.shutdown	= spdif_out_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.trigger	= spdif_out_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.hw_params	= spdif_out_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.no_capture_mute = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static struct snd_soc_dai_driver spdif_out_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		.channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		.channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		.rates = (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 				 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 				 SNDRV_PCM_RATE_192000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		.formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.probe = spdif_soc_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.ops = &spdif_out_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const struct snd_soc_component_driver spdif_out_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.name		= "spdif-out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int spdif_out_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	struct spdif_out_dev *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct spear_spdif_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	host->io_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	if (IS_ERR(host->io_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		return PTR_ERR(host->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	host->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (IS_ERR(host->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return PTR_ERR(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	host->dma_params.data = pdata->dma_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	host->dma_params.addr = res->start + SPDIF_OUT_FIFO_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	host->dma_params.max_burst = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	host->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	dev_set_drvdata(&pdev->dev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	ret = devm_snd_soc_register_component(&pdev->dev, &spdif_out_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 					      &spdif_out_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	return devm_spear_pcm_platform_register(&pdev->dev, &host->config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 						pdata->filter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int spdif_out_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	struct spdif_out_dev *host = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if (host->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		clk_disable(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int spdif_out_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	struct spdif_out_dev *host = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (host->running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		clk_enable(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		spdif_out_configure(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		spdif_out_clock(host, host->saved_params.core_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 				host->saved_params.rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static SIMPLE_DEV_PM_OPS(spdif_out_dev_pm_ops, spdif_out_suspend, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		spdif_out_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SPDIF_OUT_DEV_PM_OPS (&spdif_out_dev_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SPDIF_OUT_DEV_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static struct platform_driver spdif_out_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	.probe		= spdif_out_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		.name	= "spdif-out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		.pm	= SPDIF_OUT_DEV_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) module_platform_driver(spdif_out_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MODULE_DESCRIPTION("SPEAr SPDIF OUT SoC Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MODULE_ALIAS("platform:spdif_out");