^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright(c) 2018 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __SOUND_SOC_SOF_PRIV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __SOUND_SOC_SOF_PRIV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/hdaudio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/sof.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/sof/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/sof/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/sof/trace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <uapi/sound/sof/fw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* debug flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SOF_DBG_ENABLE_TRACE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SOF_DBG_REGS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SOF_DBG_MBOX BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SOF_DBG_TEXT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SOF_DBG_PCI BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SOF_DBG_RETAIN_CTX BIT(5) /* prevent DSP D3 on FW exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* global debug state set by SOF_DBG_ flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) extern int sof_core_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* max BARs mmaped devices can use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SND_SOF_BARS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* time in ms for runtime suspend delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SND_SOF_SUSPEND_DELAY_MS 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* DMA buffer size for trace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DMA_BUF_SIZE_FOR_TRACE (PAGE_SIZE * 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SOF_IPC_DSP_REPLY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SOF_IPC_HOST_REPLY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* convenience constructor for DAI driver streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SOF_DAI_STREAM(sname, scmin, scmax, srates, sfmt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {.stream_name = sname, .channels_min = scmin, .channels_max = scmax, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .rates = srates, .formats = sfmt}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SOF_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_FLOAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ENABLE_DEBUGFS_CACHEBUF \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) (IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* So far the primary core on all DSPs has ID 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SOF_DSP_PRIMARY_CORE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* DSP power state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum sof_dsp_power_states {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) SOF_DSP_PM_D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) SOF_DSP_PM_D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SOF_DSP_PM_D2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SOF_DSP_PM_D3_HOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SOF_DSP_PM_D3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) SOF_DSP_PM_D3_COLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct sof_dsp_power_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 substate; /* platform-specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* System suspend target state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) enum sof_system_suspend_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) SOF_SUSPEND_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SOF_SUSPEND_S0IX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SOF_SUSPEND_S3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct snd_sof_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct snd_sof_ipc_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct snd_sof_ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct snd_sof_debugfs_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct snd_soc_tplg_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct snd_soc_component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct snd_sof_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * SOF DSP HW abstraction operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Used to abstract DSP HW architecture and any IO busses between host CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * and DSP device(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct snd_sof_dsp_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* probe and remove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int (*probe)(struct snd_sof_dev *sof_dev); /* mandatory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int (*remove)(struct snd_sof_dev *sof_dev); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* DSP core boot / reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int (*run)(struct snd_sof_dev *sof_dev); /* mandatory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int (*stall)(struct snd_sof_dev *sof_dev); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int (*reset)(struct snd_sof_dev *sof_dev); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int (*core_power_up)(struct snd_sof_dev *sof_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int core_mask); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int (*core_power_down)(struct snd_sof_dev *sof_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int core_mask); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * Register IO: only used by respective drivers themselves,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * TODO: consider removing these operations and calling respective
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * implementations directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void (*write)(struct snd_sof_dev *sof_dev, void __iomem *addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 value); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 (*read)(struct snd_sof_dev *sof_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void __iomem *addr); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) void (*write64)(struct snd_sof_dev *sof_dev, void __iomem *addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u64 value); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u64 (*read64)(struct snd_sof_dev *sof_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void __iomem *addr); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* memcpy IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void (*block_read)(struct snd_sof_dev *sof_dev, u32 bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 offset, void *dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) size_t size); /* mandatory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void (*block_write)(struct snd_sof_dev *sof_dev, u32 bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 offset, void *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) size_t size); /* mandatory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) irqreturn_t (*irq_handler)(int irq, void *context); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) irqreturn_t (*irq_thread)(int irq, void *context); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* ipc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int (*send_msg)(struct snd_sof_dev *sof_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct snd_sof_ipc_msg *msg); /* mandatory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* FW loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int (*load_firmware)(struct snd_sof_dev *sof_dev); /* mandatory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int (*load_module)(struct snd_sof_dev *sof_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct snd_sof_mod_hdr *hdr); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * FW ready checks for ABI compatibility and creates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * memory windows at first boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int (*fw_ready)(struct snd_sof_dev *sdev, u32 msg_id); /* mandatory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* connect pcm substream to a host stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int (*pcm_open)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct snd_pcm_substream *substream); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* disconnect pcm substream to a host stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int (*pcm_close)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct snd_pcm_substream *substream); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* host stream hw params */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int (*pcm_hw_params)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct sof_ipc_stream_params *ipc_params); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* host stream hw_free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int (*pcm_hw_free)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct snd_pcm_substream *substream); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* host stream trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int (*pcm_trigger)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int cmd); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* host stream pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) snd_pcm_uframes_t (*pcm_pointer)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct snd_pcm_substream *substream); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_PROBES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Except for probe_pointer, all probe ops are mandatory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int (*probe_assign)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct snd_compr_stream *cstream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct snd_soc_dai *dai); /* mandatory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int (*probe_free)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct snd_compr_stream *cstream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct snd_soc_dai *dai); /* mandatory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int (*probe_set_params)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct snd_compr_stream *cstream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct snd_compr_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct snd_soc_dai *dai); /* mandatory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int (*probe_trigger)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct snd_compr_stream *cstream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct snd_soc_dai *dai); /* mandatory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int (*probe_pointer)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct snd_compr_stream *cstream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct snd_compr_tstamp *tstamp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct snd_soc_dai *dai); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* host read DSP stream data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) void (*ipc_msg_data)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void *p, size_t sz); /* mandatory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* host configure DSP HW parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int (*ipc_pcm_params)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) const struct sof_ipc_pcm_params_reply *reply); /* mandatory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* pre/post firmware run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int (*pre_fw_run)(struct snd_sof_dev *sof_dev); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int (*post_fw_run)(struct snd_sof_dev *sof_dev); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* DSP PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int (*suspend)(struct snd_sof_dev *sof_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 target_state); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int (*resume)(struct snd_sof_dev *sof_dev); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int (*runtime_suspend)(struct snd_sof_dev *sof_dev); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int (*runtime_resume)(struct snd_sof_dev *sof_dev); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int (*runtime_idle)(struct snd_sof_dev *sof_dev); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int (*set_hw_params_upon_resume)(struct snd_sof_dev *sdev); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int (*set_power_state)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) const struct sof_dsp_power_state *target_state); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* DSP clocking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int (*set_clk)(struct snd_sof_dev *sof_dev, u32 freq); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) const struct snd_sof_debugfs_map *debug_map; /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int debug_map_count; /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) void (*dbg_dump)(struct snd_sof_dev *sof_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 flags); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) void (*ipc_dump)(struct snd_sof_dev *sof_dev); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* host DMA trace initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int (*trace_init)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 *stream_tag); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int (*trace_release)(struct snd_sof_dev *sdev); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int (*trace_trigger)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int cmd); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* misc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int (*get_bar_index)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 type); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int (*get_mailbox_offset)(struct snd_sof_dev *sdev);/* mandatory for common loader code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int (*get_window_offset)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 id);/* mandatory for common loader code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* machine driver ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int (*machine_register)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void *pdata); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) void (*machine_unregister)(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) void *pdata); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) void (*machine_select)(struct snd_sof_dev *sdev); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) void (*set_mach_params)(const struct snd_soc_acpi_mach *mach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct device *dev); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* DAI ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct snd_soc_dai_driver *drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int num_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* ALSA HW info flags, will be stored in snd_pcm_runtime.hw.info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 hw_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) const struct sof_arch_ops *arch_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* DSP architecture specific callbacks for oops and stack dumps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct sof_arch_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) void (*dsp_oops)(struct snd_sof_dev *sdev, void *oops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) void (*dsp_stack)(struct snd_sof_dev *sdev, void *oops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 *stack, u32 stack_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define sof_arch_ops(sdev) ((sdev)->pdata->desc->ops->arch_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* DSP device HW descriptor mapping between bus ID and ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct sof_ops_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) const struct sof_dev_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) const struct snd_sof_dsp_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) enum sof_dfsentry_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) SOF_DFSENTRY_TYPE_IOMEM = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) SOF_DFSENTRY_TYPE_BUF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) enum sof_debugfs_access_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) SOF_DEBUGFS_ACCESS_ALWAYS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) SOF_DEBUGFS_ACCESS_D0_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* FS entry for debug files that can expose DSP memories, registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct snd_sof_dfsentry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) enum sof_dfsentry_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * access_type specifies if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * memory -> DSP resource (memory, register etc) is always accessible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * or if it is accessible only when the DSP is in D0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) enum sof_debugfs_access_type access_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #if ENABLE_DEBUGFS_CACHEBUF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) char *cache_buf; /* buffer to cache the contents of debugfs memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct snd_sof_dev *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct list_head list; /* list in sdev dfsentry list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) void __iomem *io_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Debug mapping for any DSP memory or registers that can used for debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct snd_sof_debugfs_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * access_type specifies if the memory is always accessible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * or if it is accessible only when the DSP is in D0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) enum sof_debugfs_access_type access_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* mailbox descriptor, used for host <-> DSP IPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct snd_sof_mailbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* IPC message descriptor for host <-> DSP IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct snd_sof_ipc_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* message data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) void *msg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) void *reply_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) size_t msg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) size_t reply_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int reply_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) wait_queue_head_t waitq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bool ipc_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) enum snd_sof_fw_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) SOF_FW_BOOT_NOT_STARTED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) SOF_FW_BOOT_PREPARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) SOF_FW_BOOT_IN_PROGRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) SOF_FW_BOOT_FAILED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) SOF_FW_BOOT_READY_FAILED, /* firmware booted but fw_ready op failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) SOF_FW_BOOT_COMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * SOF Device Level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct snd_sof_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) spinlock_t ipc_lock; /* lock for IPC users */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) spinlock_t hw_lock; /* lock for HW IO access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * ASoC components. plat_drv fields are set dynamically so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * can't use const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct snd_soc_component_driver plat_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* current DSP power state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct sof_dsp_power_state dsp_power_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Intended power target of system suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) enum sof_system_suspend_state system_suspend_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* DSP firmware boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) wait_queue_head_t boot_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) enum snd_sof_fw_state fw_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) bool first_boot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* work queue in case the probe is implemented in two steps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct work_struct probe_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* DSP HW differentiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct snd_sof_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* IPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct snd_sof_ipc *ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct snd_sof_mailbox dsp_box; /* DSP initiated IPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct snd_sof_mailbox host_box; /* Host initiated IPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct snd_sof_mailbox stream_box; /* Stream position update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct snd_sof_mailbox debug_box; /* Debug info updates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct snd_sof_ipc_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int ipc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 next_comp_id; /* monotonic - reset during S3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* memory bases for mmaped DSPs - set by dsp_init() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) void __iomem *bar[SND_SOF_BARS]; /* DSP base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int mmio_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int mailbox_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) size_t dsp_oops_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct dentry *debugfs_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct list_head dfsentry_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* firmware loader */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct snd_dma_buffer dmab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct snd_dma_buffer dmab_bdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct sof_ipc_fw_ready fw_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct sof_ipc_fw_version fw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct sof_ipc_cc_version *cc_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* topology */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct snd_soc_tplg_ops *tplg_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct list_head pcm_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct list_head kcontrol_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct list_head widget_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct list_head dai_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct list_head route_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct snd_soc_component *component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 enabled_cores_mask; /* keep track of enabled cores */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* FW configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct sof_ipc_window *info_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* IPC timeouts in ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int ipc_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int boot_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_PROBES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned int extractor_stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* DMA for Trace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct snd_dma_buffer dmatb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct snd_dma_buffer dmatp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int dma_trace_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) wait_queue_head_t trace_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 host_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) bool dtrace_is_supported; /* set with Kconfig or module parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) bool dtrace_is_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) bool dtrace_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) bool dtrace_draining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) bool msi_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) void *private; /* core does not touch this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * Device Level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int snd_sof_device_probe(struct device *dev, struct snd_sof_pdata *plat_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int snd_sof_device_remove(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int snd_sof_runtime_suspend(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int snd_sof_runtime_resume(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int snd_sof_runtime_idle(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int snd_sof_resume(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int snd_sof_suspend(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int snd_sof_dsp_power_down_notify(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int snd_sof_prepare(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) void snd_sof_complete(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) void snd_sof_new_platform_drv(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int snd_sof_create_page_table(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct snd_dma_buffer *dmab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) unsigned char *page_table, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * Firmware loading.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int snd_sof_load_firmware(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int snd_sof_load_firmware_raw(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int snd_sof_load_firmware_memcpy(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) int snd_sof_run_firmware(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int snd_sof_parse_module_memcpy(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct snd_sof_mod_hdr *module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) void snd_sof_fw_unload(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int snd_sof_fw_parse_ext_data(struct snd_sof_dev *sdev, u32 bar, u32 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * IPC low level APIs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct snd_sof_ipc *snd_sof_ipc_init(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) void snd_sof_ipc_free(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) void snd_sof_ipc_reply(struct snd_sof_dev *sdev, u32 msg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) void snd_sof_ipc_msgs_rx(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int snd_sof_ipc_stream_pcm_params(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct sof_ipc_pcm_params *params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int snd_sof_dsp_mailbox_init(struct snd_sof_dev *sdev, u32 dspbox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) size_t dspbox_size, u32 hostbox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) size_t hostbox_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int snd_sof_ipc_valid(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int sof_ipc_tx_message(struct snd_sof_ipc *ipc, u32 header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) void *msg_data, size_t msg_bytes, void *reply_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) size_t reply_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int sof_ipc_tx_message_no_pm(struct snd_sof_ipc *ipc, u32 header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) void *msg_data, size_t msg_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) void *reply_data, size_t reply_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * Trace/debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int snd_sof_init_trace(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) void snd_sof_release_trace(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) void snd_sof_free_trace(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int snd_sof_dbg_init(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) void snd_sof_free_debug(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int snd_sof_debugfs_io_item(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) void __iomem *base, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) enum sof_debugfs_access_type access_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int snd_sof_debugfs_buf_item(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) void *base, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) const char *name, mode_t mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int snd_sof_trace_update_pos(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct sof_ipc_dma_trace_posn *posn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) void snd_sof_trace_notify_for_error(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) void snd_sof_get_status(struct snd_sof_dev *sdev, u32 panic_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u32 tracep_code, void *oops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct sof_ipc_panic_info *panic_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) void *stack, size_t stack_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int snd_sof_init_trace_ipc(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) void snd_sof_handle_fw_exception(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * Platform specific ops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) extern struct snd_compress_ops sof_compressed_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * DSP Architectures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static inline void sof_stack(struct snd_sof_dev *sdev, void *oops, u32 *stack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u32 stack_words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) sof_arch_ops(sdev)->dsp_stack(sdev, oops, stack, stack_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static inline void sof_oops(struct snd_sof_dev *sdev, void *oops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (sof_arch_ops(sdev)->dsp_oops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) sof_arch_ops(sdev)->dsp_oops(sdev, oops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) extern const struct sof_arch_ops sof_xtensa_arch_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * Utilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) void sof_io_write(struct snd_sof_dev *sdev, void __iomem *addr, u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) void sof_io_write64(struct snd_sof_dev *sdev, void __iomem *addr, u64 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u32 sof_io_read(struct snd_sof_dev *sdev, void __iomem *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u64 sof_io_read64(struct snd_sof_dev *sdev, void __iomem *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) void sof_mailbox_write(struct snd_sof_dev *sdev, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) void *message, size_t bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) void sof_mailbox_read(struct snd_sof_dev *sdev, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) void *message, size_t bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) void sof_block_write(struct snd_sof_dev *sdev, u32 bar, u32 offset, void *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) void sof_block_read(struct snd_sof_dev *sdev, u32 bar, u32 offset, void *dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int sof_fw_ready(struct snd_sof_dev *sdev, u32 msg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) void intel_ipc_msg_data(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) void *p, size_t sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int intel_ipc_pcm_params(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) const struct sof_ipc_pcm_params_reply *reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int intel_pcm_open(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct snd_pcm_substream *substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) int intel_pcm_close(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct snd_pcm_substream *substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int sof_machine_check(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define sof_dev_dbg_or_err(dev, is_err, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (is_err) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dev_err(dev, "error: " fmt, __VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dev_dbg(dev, fmt, __VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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