^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright(c) 2018 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) // Generic IPC layer that can work over MMIO and SPI/I2C. PHY layer provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) // by platform driver code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "sof-priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "sof-audio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static void ipc_trace_message(struct snd_sof_dev *sdev, u32 msg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static void ipc_stream_message(struct snd_sof_dev *sdev, u32 msg_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * IPC message Tx/Rx message handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* SOF generic IPC data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct snd_sof_ipc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct snd_sof_dev *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* protects messages and the disable flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct mutex tx_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* disables further sending of ipc's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) bool disable_ipc_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct snd_sof_ipc_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct sof_ipc_ctrl_data_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) size_t msg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) size_t hdr_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) size_t pl_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) size_t elems;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 num_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u8 *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 *dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_VERBOSE_IPC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void ipc_log_header(struct device *dev, u8 *text, u32 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 *str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 *str2 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 glb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) bool vdbg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) glb = cmd & SOF_GLB_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) type = cmd & SOF_CMD_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) switch (glb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) case SOF_IPC_GLB_REPLY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) str = "GLB_REPLY"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) case SOF_IPC_GLB_COMPOUND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) str = "GLB_COMPOUND"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) case SOF_IPC_GLB_TPLG_MSG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) str = "GLB_TPLG_MSG";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case SOF_IPC_TPLG_COMP_NEW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) str2 = "COMP_NEW"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case SOF_IPC_TPLG_COMP_FREE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) str2 = "COMP_FREE"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case SOF_IPC_TPLG_COMP_CONNECT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) str2 = "COMP_CONNECT"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case SOF_IPC_TPLG_PIPE_NEW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) str2 = "PIPE_NEW"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case SOF_IPC_TPLG_PIPE_FREE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) str2 = "PIPE_FREE"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case SOF_IPC_TPLG_PIPE_CONNECT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) str2 = "PIPE_CONNECT"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case SOF_IPC_TPLG_PIPE_COMPLETE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) str2 = "PIPE_COMPLETE"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case SOF_IPC_TPLG_BUFFER_NEW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) str2 = "BUFFER_NEW"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case SOF_IPC_TPLG_BUFFER_FREE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) str2 = "BUFFER_FREE"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) str2 = "unknown type"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case SOF_IPC_GLB_PM_MSG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) str = "GLB_PM_MSG";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case SOF_IPC_PM_CTX_SAVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) str2 = "CTX_SAVE"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case SOF_IPC_PM_CTX_RESTORE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) str2 = "CTX_RESTORE"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case SOF_IPC_PM_CTX_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) str2 = "CTX_SIZE"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case SOF_IPC_PM_CLK_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) str2 = "CLK_SET"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) case SOF_IPC_PM_CLK_GET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) str2 = "CLK_GET"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case SOF_IPC_PM_CLK_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) str2 = "CLK_REQ"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case SOF_IPC_PM_CORE_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) str2 = "CORE_ENABLE"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) str2 = "unknown type"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case SOF_IPC_GLB_COMP_MSG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) str = "GLB_COMP_MSG";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case SOF_IPC_COMP_SET_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) str2 = "SET_VALUE"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case SOF_IPC_COMP_GET_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) str2 = "GET_VALUE"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case SOF_IPC_COMP_SET_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) str2 = "SET_DATA"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case SOF_IPC_COMP_GET_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) str2 = "GET_DATA"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) str2 = "unknown type"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case SOF_IPC_GLB_STREAM_MSG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) str = "GLB_STREAM_MSG";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case SOF_IPC_STREAM_PCM_PARAMS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) str2 = "PCM_PARAMS"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case SOF_IPC_STREAM_PCM_PARAMS_REPLY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) str2 = "PCM_REPLY"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case SOF_IPC_STREAM_PCM_FREE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) str2 = "PCM_FREE"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case SOF_IPC_STREAM_TRIG_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) str2 = "TRIG_START"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case SOF_IPC_STREAM_TRIG_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) str2 = "TRIG_STOP"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case SOF_IPC_STREAM_TRIG_PAUSE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) str2 = "TRIG_PAUSE"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case SOF_IPC_STREAM_TRIG_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) str2 = "TRIG_RELEASE"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case SOF_IPC_STREAM_TRIG_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) str2 = "TRIG_DRAIN"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case SOF_IPC_STREAM_TRIG_XRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) str2 = "TRIG_XRUN"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case SOF_IPC_STREAM_POSITION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) vdbg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) str2 = "POSITION"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case SOF_IPC_STREAM_VORBIS_PARAMS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) str2 = "VORBIS_PARAMS"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) case SOF_IPC_STREAM_VORBIS_FREE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) str2 = "VORBIS_FREE"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) str2 = "unknown type"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case SOF_IPC_FW_READY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) str = "FW_READY"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case SOF_IPC_GLB_DAI_MSG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) str = "GLB_DAI_MSG";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case SOF_IPC_DAI_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) str2 = "CONFIG"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case SOF_IPC_DAI_LOOPBACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) str2 = "LOOPBACK"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) str2 = "unknown type"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) case SOF_IPC_GLB_TRACE_MSG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) str = "GLB_TRACE_MSG"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case SOF_IPC_GLB_TEST_MSG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) str = "GLB_TEST_MSG";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case SOF_IPC_TEST_IPC_FLOOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) str2 = "IPC_FLOOD"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) str2 = "unknown type"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) str = "unknown GLB command"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (str2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (vdbg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_vdbg(dev, "%s: 0x%x: %s: %s\n", text, cmd, str, str2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev_dbg(dev, "%s: 0x%x: %s: %s\n", text, cmd, str, str2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dev_dbg(dev, "%s: 0x%x: %s\n", text, cmd, str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static inline void ipc_log_header(struct device *dev, u8 *text, u32 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if ((cmd & SOF_GLB_TYPE_MASK) != SOF_IPC_GLB_TRACE_MSG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_dbg(dev, "%s: 0x%x\n", text, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* wait for IPC message reply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int tx_wait_done(struct snd_sof_ipc *ipc, struct snd_sof_ipc_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) void *reply_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct snd_sof_dev *sdev = ipc->sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct sof_ipc_cmd_hdr *hdr = msg->msg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* wait for DSP IPC completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = wait_event_timeout(msg->waitq, msg->ipc_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) msecs_to_jiffies(sdev->ipc_timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dev_err(sdev->dev, "error: ipc timed out for 0x%x size %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) hdr->cmd, hdr->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) snd_sof_handle_fw_exception(ipc->sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = msg->reply_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_err(sdev->dev, "error: ipc error for 0x%x size %zu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) hdr->cmd, msg->reply_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ipc_log_header(sdev->dev, "ipc tx succeeded", hdr->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (msg->reply_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* copy the data returned from DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) memcpy(reply_data, msg->reply_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) msg->reply_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* send IPC message from host to DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int sof_ipc_tx_message_unlocked(struct snd_sof_ipc *ipc, u32 header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void *msg_data, size_t msg_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) void *reply_data, size_t reply_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct snd_sof_dev *sdev = ipc->sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct snd_sof_ipc_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (ipc->disable_ipc_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * The spin-lock is also still needed to protect message objects against
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * other atomic contexts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) spin_lock_irq(&sdev->ipc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* initialise the message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) msg = &ipc->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) msg->header = header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) msg->msg_size = msg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) msg->reply_size = reply_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) msg->reply_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* attach any data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (msg_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) memcpy(msg->msg_data, msg_data, msg_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) sdev->msg = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = snd_sof_dsp_send_msg(sdev, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Next reply that we receive will be related to this message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) msg->ipc_complete = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) spin_unlock_irq(&sdev->ipc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev_err_ratelimited(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "error: ipc tx failed with error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ipc_log_header(sdev->dev, "ipc tx", msg->header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* now wait for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = tx_wait_done(ipc, msg, reply_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* send IPC message from host to DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int sof_ipc_tx_message(struct snd_sof_ipc *ipc, u32 header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) void *msg_data, size_t msg_bytes, void *reply_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) size_t reply_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) const struct sof_dsp_power_state target_state = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .state = SOF_DSP_PM_D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* ensure the DSP is in D0 before sending a new IPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret = snd_sof_dsp_set_power_state(ipc->sdev, &target_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dev_err(ipc->sdev->dev, "error: resuming DSP %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return sof_ipc_tx_message_no_pm(ipc, header, msg_data, msg_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) reply_data, reply_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) EXPORT_SYMBOL(sof_ipc_tx_message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * send IPC message from host to DSP without modifying the DSP state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * This will be used for IPC's that can be handled by the DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * even in a low-power D0 substate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int sof_ipc_tx_message_no_pm(struct snd_sof_ipc *ipc, u32 header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) void *msg_data, size_t msg_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) void *reply_data, size_t reply_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (msg_bytes > SOF_IPC_MSG_MAX_SIZE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) reply_bytes > SOF_IPC_MSG_MAX_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Serialise IPC TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mutex_lock(&ipc->tx_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = sof_ipc_tx_message_unlocked(ipc, header, msg_data, msg_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) reply_data, reply_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) mutex_unlock(&ipc->tx_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) EXPORT_SYMBOL(sof_ipc_tx_message_no_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* handle reply message from DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) void snd_sof_ipc_reply(struct snd_sof_dev *sdev, u32 msg_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct snd_sof_ipc_msg *msg = &sdev->ipc->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (msg->ipc_complete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_dbg(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "no reply expected, received 0x%x, will be ignored",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) msg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* wake up and return the error if we have waiters on this message ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) msg->ipc_complete = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) wake_up(&msg->waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) EXPORT_SYMBOL(snd_sof_ipc_reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* DSP firmware has sent host a message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) void snd_sof_ipc_msgs_rx(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct sof_ipc_cmd_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 cmd, type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* read back header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) snd_sof_ipc_msg_data(sdev, NULL, &hdr, sizeof(hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ipc_log_header(sdev->dev, "ipc rx", hdr.cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) cmd = hdr.cmd & SOF_GLB_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) type = hdr.cmd & SOF_CMD_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* check message type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) case SOF_IPC_GLB_REPLY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_err(sdev->dev, "error: ipc reply unknown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) case SOF_IPC_FW_READY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* check for FW boot completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (sdev->fw_state == SOF_FW_BOOT_IN_PROGRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) err = sof_ops(sdev)->fw_ready(sdev, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) sdev->fw_state = SOF_FW_BOOT_READY_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) sdev->fw_state = SOF_FW_BOOT_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* wake up firmware loader */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) wake_up(&sdev->boot_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case SOF_IPC_GLB_COMPOUND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case SOF_IPC_GLB_TPLG_MSG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case SOF_IPC_GLB_PM_MSG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case SOF_IPC_GLB_COMP_MSG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case SOF_IPC_GLB_STREAM_MSG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* need to pass msg id into the function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ipc_stream_message(sdev, hdr.cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case SOF_IPC_GLB_TRACE_MSG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ipc_trace_message(sdev, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dev_err(sdev->dev, "error: unknown DSP message 0x%x\n", cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ipc_log_header(sdev->dev, "ipc rx done", hdr.cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) EXPORT_SYMBOL(snd_sof_ipc_msgs_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * IPC trace mechanism.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static void ipc_trace_message(struct snd_sof_dev *sdev, u32 msg_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct sof_ipc_dma_trace_posn posn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) switch (msg_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case SOF_IPC_TRACE_DMA_POSITION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* read back full message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) snd_sof_ipc_msg_data(sdev, NULL, &posn, sizeof(posn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) snd_sof_trace_update_pos(sdev, &posn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev_err(sdev->dev, "error: unhandled trace message %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) msg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * IPC stream position.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static void ipc_period_elapsed(struct snd_sof_dev *sdev, u32 msg_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct snd_soc_component *scomp = sdev->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct snd_sof_pcm_stream *stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct sof_ipc_stream_posn posn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct snd_sof_pcm *spcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) spcm = snd_sof_find_spcm_comp(scomp, msg_id, &direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (!spcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) "error: period elapsed for unknown stream, msg_id %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) msg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) stream = &spcm->stream[direction];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) snd_sof_ipc_msg_data(sdev, stream->substream, &posn, sizeof(posn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dev_vdbg(sdev->dev, "posn : host 0x%llx dai 0x%llx wall 0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) posn.host_posn, posn.dai_posn, posn.wallclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) memcpy(&stream->posn, &posn, sizeof(posn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* only inform ALSA for period_wakeup mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (!stream->substream->runtime->no_period_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) snd_sof_pcm_period_elapsed(stream->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* DSP notifies host of an XRUN within FW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static void ipc_xrun(struct snd_sof_dev *sdev, u32 msg_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct snd_soc_component *scomp = sdev->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct snd_sof_pcm_stream *stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct sof_ipc_stream_posn posn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct snd_sof_pcm *spcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) spcm = snd_sof_find_spcm_comp(scomp, msg_id, &direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (!spcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dev_err(sdev->dev, "error: XRUN for unknown stream, msg_id %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) msg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) stream = &spcm->stream[direction];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) snd_sof_ipc_msg_data(sdev, stream->substream, &posn, sizeof(posn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) dev_dbg(sdev->dev, "posn XRUN: host %llx comp %d size %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) posn.host_posn, posn.xrun_comp_id, posn.xrun_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #if defined(CONFIG_SND_SOC_SOF_DEBUG_XRUN_STOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* stop PCM on XRUN - used for pipeline debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) memcpy(&stream->posn, &posn, sizeof(posn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) snd_pcm_stop_xrun(stream->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* stream notifications from DSP FW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static void ipc_stream_message(struct snd_sof_dev *sdev, u32 msg_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* get msg cmd type and msd id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u32 msg_type = msg_cmd & SOF_CMD_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u32 msg_id = SOF_IPC_MESSAGE_ID(msg_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) switch (msg_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) case SOF_IPC_STREAM_POSITION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ipc_period_elapsed(sdev, msg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case SOF_IPC_STREAM_TRIG_XRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ipc_xrun(sdev, msg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dev_err(sdev->dev, "error: unhandled stream message %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) msg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* get stream position IPC - use faster MMIO method if available on platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int snd_sof_ipc_stream_posn(struct snd_soc_component *scomp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct snd_sof_pcm *spcm, int direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct sof_ipc_stream_posn *posn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct sof_ipc_stream stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* read position via slower IPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) stream.hdr.size = sizeof(stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) stream.hdr.cmd = SOF_IPC_GLB_STREAM_MSG | SOF_IPC_STREAM_POSITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) stream.comp_id = spcm->stream[direction].comp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* send IPC to the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) err = sof_ipc_tx_message(sdev->ipc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) stream.hdr.cmd, &stream, sizeof(stream), posn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) sizeof(*posn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev_err(sdev->dev, "error: failed to get stream %d position\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) stream.comp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) EXPORT_SYMBOL(snd_sof_ipc_stream_posn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int sof_get_ctrl_copy_params(enum sof_ipc_ctrl_type ctrl_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct sof_ipc_ctrl_data *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct sof_ipc_ctrl_data *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct sof_ipc_ctrl_data_params *sparams)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) switch (ctrl_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) case SOF_CTRL_TYPE_VALUE_CHAN_GET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case SOF_CTRL_TYPE_VALUE_CHAN_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) sparams->src = (u8 *)src->chanv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) sparams->dst = (u8 *)dst->chanv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) case SOF_CTRL_TYPE_VALUE_COMP_GET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case SOF_CTRL_TYPE_VALUE_COMP_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) sparams->src = (u8 *)src->compv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) sparams->dst = (u8 *)dst->compv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case SOF_CTRL_TYPE_DATA_GET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case SOF_CTRL_TYPE_DATA_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) sparams->src = (u8 *)src->data->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) sparams->dst = (u8 *)dst->data->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* calculate payload size and number of messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) sparams->pl_size = SOF_IPC_MSG_MAX_SIZE - sparams->hdr_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) sparams->num_msg = DIV_ROUND_UP(sparams->msg_bytes, sparams->pl_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int sof_set_get_large_ctrl_data(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct sof_ipc_ctrl_data *cdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct sof_ipc_ctrl_data_params *sparams,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) bool send)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct sof_ipc_ctrl_data *partdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) size_t send_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) size_t offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) size_t msg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) size_t pl_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* allocate max ipc size because we have at least one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) partdata = kzalloc(SOF_IPC_MSG_MAX_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (!partdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (send)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) err = sof_get_ctrl_copy_params(cdata->type, cdata, partdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) sparams);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) err = sof_get_ctrl_copy_params(cdata->type, partdata, cdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) sparams);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) kfree(partdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) msg_bytes = sparams->msg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) pl_size = sparams->pl_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* copy the header data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) memcpy(partdata, cdata, sparams->hdr_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* Serialise IPC TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) mutex_lock(&sdev->ipc->tx_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* copy the payload data in a loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) for (i = 0; i < sparams->num_msg; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) send_bytes = min(msg_bytes, pl_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) partdata->num_elems = send_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) partdata->rhdr.hdr.size = sparams->hdr_bytes + send_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) partdata->msg_index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) msg_bytes -= send_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) partdata->elems_remaining = msg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (send)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) memcpy(sparams->dst, sparams->src + offset, send_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) err = sof_ipc_tx_message_unlocked(sdev->ipc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) partdata->rhdr.hdr.cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) partdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) partdata->rhdr.hdr.size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) partdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) partdata->rhdr.hdr.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (!send)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) memcpy(sparams->dst + offset, sparams->src, send_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) offset += pl_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) mutex_unlock(&sdev->ipc->tx_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) kfree(partdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * IPC get()/set() for kcontrols.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int snd_sof_ipc_set_get_comp_data(struct snd_sof_control *scontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) u32 ipc_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) enum sof_ipc_ctrl_type ctrl_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) enum sof_ipc_ctrl_cmd ctrl_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) bool send)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct snd_soc_component *scomp = scontrol->scomp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct sof_ipc_ctrl_data *cdata = scontrol->control_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(scomp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct sof_ipc_fw_ready *ready = &sdev->fw_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct sof_ipc_fw_version *v = &ready->version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct sof_ipc_ctrl_data_params sparams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) size_t send_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* read or write firmware volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (scontrol->readback_offset != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* write/read value header via mmaped region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) send_bytes = sizeof(struct sof_ipc_ctrl_value_chan) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) cdata->num_elems;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (send)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) snd_sof_dsp_block_write(sdev, sdev->mmio_bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) scontrol->readback_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) cdata->chanv, send_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) snd_sof_dsp_block_read(sdev, sdev->mmio_bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) scontrol->readback_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) cdata->chanv, send_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) cdata->rhdr.hdr.cmd = SOF_IPC_GLB_COMP_MSG | ipc_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) cdata->cmd = ctrl_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) cdata->type = ctrl_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) cdata->comp_id = scontrol->comp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) cdata->msg_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* calculate header and data size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) switch (cdata->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case SOF_CTRL_TYPE_VALUE_CHAN_GET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) case SOF_CTRL_TYPE_VALUE_CHAN_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) sparams.msg_bytes = scontrol->num_channels *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) sizeof(struct sof_ipc_ctrl_value_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) sparams.hdr_bytes = sizeof(struct sof_ipc_ctrl_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) sparams.elems = scontrol->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) case SOF_CTRL_TYPE_VALUE_COMP_GET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) case SOF_CTRL_TYPE_VALUE_COMP_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) sparams.msg_bytes = scontrol->num_channels *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) sizeof(struct sof_ipc_ctrl_value_comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) sparams.hdr_bytes = sizeof(struct sof_ipc_ctrl_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) sparams.elems = scontrol->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) case SOF_CTRL_TYPE_DATA_GET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) case SOF_CTRL_TYPE_DATA_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) sparams.msg_bytes = cdata->data->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) sparams.hdr_bytes = sizeof(struct sof_ipc_ctrl_data) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) sizeof(struct sof_abi_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) sparams.elems = cdata->data->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) cdata->rhdr.hdr.size = sparams.msg_bytes + sparams.hdr_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) cdata->num_elems = sparams.elems;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) cdata->elems_remaining = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* send normal size ipc in one part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (cdata->rhdr.hdr.size <= SOF_IPC_MSG_MAX_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) err = sof_ipc_tx_message(sdev->ipc, cdata->rhdr.hdr.cmd, cdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) cdata->rhdr.hdr.size, cdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) cdata->rhdr.hdr.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) dev_err(sdev->dev, "error: set/get ctrl ipc comp %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) cdata->comp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* data is bigger than max ipc size, chop into smaller pieces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dev_dbg(sdev->dev, "large ipc size %u, control size %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) cdata->rhdr.hdr.size, scontrol->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* large messages is only supported from ABI 3.3.0 onwards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (v->abi_version < SOF_ABI_VER(3, 3, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dev_err(sdev->dev, "error: incompatible FW ABI version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) err = sof_set_get_large_ctrl_data(sdev, cdata, &sparams, send);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dev_err(sdev->dev, "error: set/get large ctrl ipc comp %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) cdata->comp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) EXPORT_SYMBOL(snd_sof_ipc_set_get_comp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * IPC layer enumeration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) int snd_sof_dsp_mailbox_init(struct snd_sof_dev *sdev, u32 dspbox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) size_t dspbox_size, u32 hostbox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) size_t hostbox_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) sdev->dsp_box.offset = dspbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) sdev->dsp_box.size = dspbox_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) sdev->host_box.offset = hostbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) sdev->host_box.size = hostbox_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) EXPORT_SYMBOL(snd_sof_dsp_mailbox_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) int snd_sof_ipc_valid(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct sof_ipc_fw_ready *ready = &sdev->fw_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct sof_ipc_fw_version *v = &ready->version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dev_info(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) "Firmware info: version %d:%d:%d-%s\n", v->major, v->minor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) v->micro, v->tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) dev_info(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) "Firmware: ABI %d:%d:%d Kernel ABI %d:%d:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) SOF_ABI_VERSION_MAJOR(v->abi_version),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) SOF_ABI_VERSION_MINOR(v->abi_version),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) SOF_ABI_VERSION_PATCH(v->abi_version),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) SOF_ABI_MAJOR, SOF_ABI_MINOR, SOF_ABI_PATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (SOF_ABI_VERSION_INCOMPATIBLE(SOF_ABI_VERSION, v->abi_version)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) dev_err(sdev->dev, "error: incompatible FW ABI version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (v->abi_version > SOF_ABI_VERSION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (!IS_ENABLED(CONFIG_SND_SOC_SOF_STRICT_ABI_CHECKS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) dev_warn(sdev->dev, "warn: FW ABI is more recent than kernel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev_err(sdev->dev, "error: FW ABI is more recent than kernel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (ready->flags & SOF_IPC_INFO_BUILD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev_info(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) "Firmware debug build %d on %s-%s - options:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) " GDB: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) " lock debug: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) " lock vdebug: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) v->build, v->date, v->time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) (ready->flags & SOF_IPC_INFO_GDB) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) "enabled" : "disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) (ready->flags & SOF_IPC_INFO_LOCKS) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) "enabled" : "disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) (ready->flags & SOF_IPC_INFO_LOCKSV) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* copy the fw_version into debugfs at first boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) memcpy(&sdev->fw_version, v, sizeof(*v));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) EXPORT_SYMBOL(snd_sof_ipc_valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct snd_sof_ipc *snd_sof_ipc_init(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct snd_sof_ipc *ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct snd_sof_ipc_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ipc = devm_kzalloc(sdev->dev, sizeof(*ipc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (!ipc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) mutex_init(&ipc->tx_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ipc->sdev = sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) msg = &ipc->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* indicate that we aren't sending a message ATM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) msg->ipc_complete = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* pre-allocate message data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) msg->msg_data = devm_kzalloc(sdev->dev, SOF_IPC_MSG_MAX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (!msg->msg_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) msg->reply_data = devm_kzalloc(sdev->dev, SOF_IPC_MSG_MAX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (!msg->reply_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) init_waitqueue_head(&msg->waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) EXPORT_SYMBOL(snd_sof_ipc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) void snd_sof_ipc_free(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct snd_sof_ipc *ipc = sdev->ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (!ipc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* disable sending of ipc's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) mutex_lock(&ipc->tx_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ipc->disable_ipc_tx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) mutex_unlock(&ipc->tx_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) EXPORT_SYMBOL(snd_sof_ipc_free);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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