^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright(c) 2020 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Hardware interface for audio DSP on Tigerlake.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "../ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "hda.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "hda-ipc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "../sof-audio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Tigerlake ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) const struct snd_sof_dsp_ops sof_tgl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* probe and remove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .probe = hda_dsp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .remove = hda_dsp_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Register IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .write = sof_io_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .read = sof_io_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .write64 = sof_io_write64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .read64 = sof_io_read64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Block IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .block_read = sof_block_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .block_write = sof_block_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .irq_thread = cnl_ipc_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* ipc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .send_msg = cnl_ipc_send_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .fw_ready = sof_fw_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .get_window_offset = hda_dsp_ipc_get_window_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .ipc_msg_data = hda_ipc_msg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .ipc_pcm_params = hda_ipc_pcm_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* machine driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .machine_select = hda_machine_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .machine_register = sof_machine_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .machine_unregister = sof_machine_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .set_mach_params = hda_set_mach_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .debug_map = tgl_dsp_debugfs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .dbg_dump = hda_dsp_dump,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .ipc_dump = cnl_ipc_dump,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* stream callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .pcm_open = hda_dsp_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .pcm_close = hda_dsp_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .pcm_hw_params = hda_dsp_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .pcm_hw_free = hda_dsp_stream_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .pcm_trigger = hda_dsp_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .pcm_pointer = hda_dsp_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* probe callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .probe_assign = hda_probe_compr_assign,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .probe_free = hda_probe_compr_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .probe_set_params = hda_probe_compr_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .probe_trigger = hda_probe_compr_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .probe_pointer = hda_probe_compr_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* firmware loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .load_firmware = snd_sof_load_firmware_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* pre/post fw run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .pre_fw_run = hda_dsp_pre_fw_run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .post_fw_run = hda_dsp_post_fw_run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* dsp core power up/down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .core_power_up = hda_dsp_enable_core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .core_power_down = hda_dsp_core_reset_power_down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* firmware run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .run = hda_dsp_cl_boot_firmware_iccmax,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* trace callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .trace_init = hda_dsp_trace_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .trace_release = hda_dsp_trace_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .trace_trigger = hda_dsp_trace_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* DAI drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .drv = skl_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .num_drv = SOF_SKL_NUM_DAIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .suspend = hda_dsp_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .resume = hda_dsp_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .runtime_suspend = hda_dsp_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .runtime_resume = hda_dsp_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .runtime_idle = hda_dsp_runtime_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .set_power_state = hda_dsp_set_power_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* ALSA HW info flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .hw_info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .arch_ops = &sof_xtensa_arch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) const struct sof_intel_dsp_desc tgl_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Tigerlake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .cores_num = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .init_core_mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .host_managed_cores_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .ipc_req = CNL_DSP_REG_HIPCIDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .ipc_ack = CNL_DSP_REG_HIPCIDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .ipc_ctl = CNL_DSP_REG_HIPCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .rom_init_timeout = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .ssp_count = ICL_SSP_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .ssp_base_offset = CNL_SSP_BASE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const struct sof_intel_dsp_desc tglh_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Tigerlake-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .cores_num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .init_core_mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .host_managed_cores_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .ipc_req = CNL_DSP_REG_HIPCIDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .ipc_ack = CNL_DSP_REG_HIPCIDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .ipc_ctl = CNL_DSP_REG_HIPCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .rom_init_timeout = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .ssp_count = ICL_SSP_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .ssp_base_offset = CNL_SSP_BASE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);