Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * This file is provided under a dual BSD/GPLv2 license.  When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright(c) 2017 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #ifndef __SOF_INTEL_SHIM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define __SOF_INTEL_SHIM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * SHIM registers for BYT, BSW, CHT, BDW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SHIM_CSR		(SHIM_OFFSET + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SHIM_PISR		(SHIM_OFFSET + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define SHIM_PIMR		(SHIM_OFFSET + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SHIM_ISRX		(SHIM_OFFSET + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SHIM_ISRD		(SHIM_OFFSET + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SHIM_IMRX		(SHIM_OFFSET + 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SHIM_IMRD		(SHIM_OFFSET + 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SHIM_IPCX		(SHIM_OFFSET + 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SHIM_IPCD		(SHIM_OFFSET + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SHIM_ISRSC		(SHIM_OFFSET + 0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SHIM_ISRLPESC		(SHIM_OFFSET + 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SHIM_IMRSC		(SHIM_OFFSET + 0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SHIM_IMRLPESC		(SHIM_OFFSET + 0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SHIM_IPCSC		(SHIM_OFFSET + 0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SHIM_IPCLPESC		(SHIM_OFFSET + 0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SHIM_CLKCTL		(SHIM_OFFSET + 0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SHIM_CSR2		(SHIM_OFFSET + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SHIM_LTRC		(SHIM_OFFSET + 0xE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SHIM_HMDC		(SHIM_OFFSET + 0xE8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SHIM_PWMCTRL		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * SST SHIM register bits for BYT, BSW, CHT, BDW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * Register bit naming and functionaility can differ between devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* CSR / CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SHIM_CSR_RST		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SHIM_CSR_SBCS0		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SHIM_CSR_SBCS1		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SHIM_CSR_DCS(x)		((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SHIM_CSR_DCS_MASK	(0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SHIM_CSR_STALL		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SHIM_CSR_S0IOCS		BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SHIM_CSR_S1IOCS		BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SHIM_CSR_LPCS		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SHIM_CSR_24MHZ_LPCS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	(SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1 | SHIM_CSR_LPCS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SHIM_CSR_24MHZ_NO_LPCS	(SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SHIM_BYT_CSR_RST	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SHIM_BYT_CSR_VECTOR_SEL	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SHIM_BYT_CSR_STALL	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SHIM_BYT_CSR_PWAITMODE	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /*  ISRX / ISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SHIM_ISRX_BUSY		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SHIM_ISRX_DONE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define SHIM_BYT_ISRX_REQUEST	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /*  ISRD / ISD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define SHIM_ISRD_BUSY		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define SHIM_ISRD_DONE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* IMRX / IMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define SHIM_IMRX_BUSY		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define SHIM_IMRX_DONE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define SHIM_BYT_IMRX_REQUEST	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /* IMRD / IMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define SHIM_IMRD_DONE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define SHIM_IMRD_BUSY		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define SHIM_IMRD_SSP0		BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define SHIM_IMRD_DMAC0		BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define SHIM_IMRD_DMAC1		BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define SHIM_IMRD_DMAC		(SHIM_IMRD_DMAC0 | SHIM_IMRD_DMAC1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /*  IPCX / IPCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define	SHIM_IPCX_DONE		BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define	SHIM_IPCX_BUSY		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define SHIM_BYT_IPCX_DONE	BIT_ULL(62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define SHIM_BYT_IPCX_BUSY	BIT_ULL(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /*  IPCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define	SHIM_IPCD_DONE		BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define	SHIM_IPCD_BUSY		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define SHIM_BYT_IPCD_DONE	BIT_ULL(62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define SHIM_BYT_IPCD_BUSY	BIT_ULL(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /* CLKCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define SHIM_CLKCTL_SMOS(x)	((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define SHIM_CLKCTL_MASK	(3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SHIM_CLKCTL_DCPLCG	BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SHIM_CLKCTL_SCOE1	BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SHIM_CLKCTL_SCOE0	BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* CSR2 / CS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SHIM_CSR2_SDFD_SSP0	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SHIM_CSR2_SDFD_SSP1	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* LTRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SHIM_LTRC_VAL(x)	((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* HMDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SHIM_HMDC_HDDA0(x)	((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SHIM_HMDC_HDDA1(x)	((x) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SHIM_HMDC_HDDA_E0_CH0	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SHIM_HMDC_HDDA_E0_CH1	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SHIM_HMDC_HDDA_E0_CH2	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SHIM_HMDC_HDDA_E0_CH3	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SHIM_HMDC_HDDA_E1_CH0	SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SHIM_HMDC_HDDA_E1_CH1	SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SHIM_HMDC_HDDA_E1_CH2	SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SHIM_HMDC_HDDA_E1_CH3	SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SHIM_HMDC_HDDA_E0_ALLCH	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	(SHIM_HMDC_HDDA_E0_CH0 | SHIM_HMDC_HDDA_E0_CH1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	 SHIM_HMDC_HDDA_E0_CH2 | SHIM_HMDC_HDDA_E0_CH3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SHIM_HMDC_HDDA_E1_ALLCH	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	(SHIM_HMDC_HDDA_E1_CH0 | SHIM_HMDC_HDDA_E1_CH1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	 SHIM_HMDC_HDDA_E1_CH2 | SHIM_HMDC_HDDA_E1_CH3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Audio DSP PCI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PCI_VDRTCTL0		0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PCI_VDRTCTL1		0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PCI_VDRTCTL2		0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PCI_VDRTCTL3		0xaC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* VDRTCTL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PCI_VDRTCL0_D3PGD		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PCI_VDRTCL0_D3SRAMPGD		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PCI_VDRTCL0_DSRAMPGE_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PCI_VDRTCL0_DSRAMPGE_MASK	GENMASK(PCI_VDRTCL0_DSRAMPGE_SHIFT + 19,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 						PCI_VDRTCL0_DSRAMPGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PCI_VDRTCL0_ISRAMPGE_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PCI_VDRTCL0_ISRAMPGE_MASK	GENMASK(PCI_VDRTCL0_ISRAMPGE_SHIFT + 9,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 						PCI_VDRTCL0_ISRAMPGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* VDRTCTL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PCI_VDRTCL2_DCLCGE		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PCI_VDRTCL2_DTCGE		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PCI_VDRTCL2_APLLSE_MASK		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* PMCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PCI_PMCS		0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PCI_PMCS_PS_MASK	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* DSP hardware descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct sof_intel_dsp_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	int cores_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	int host_managed_cores_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	int init_core_mask; /* cores available after fw boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	int ipc_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	int ipc_req_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	int ipc_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	int ipc_ack_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int ipc_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	int rom_init_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	int ssp_count;			/* ssp count of the platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	int ssp_base_offset;		/* base address of the SSPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) extern const struct snd_sof_dsp_ops sof_tng_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) extern const struct snd_sof_dsp_ops sof_byt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) extern const struct snd_sof_dsp_ops sof_cht_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) extern const struct snd_sof_dsp_ops sof_bdw_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) extern const struct sof_intel_dsp_desc byt_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) extern const struct sof_intel_dsp_desc cht_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) extern const struct sof_intel_dsp_desc bdw_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) extern const struct sof_intel_dsp_desc tng_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct sof_intel_stream {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	size_t posn_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #endif