^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright(c) 2017 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __SOF_INTEL_HDA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __SOF_INTEL_HDA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/soundwire/sdw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/soundwire/sdw_intel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/compress_driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/hda_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/hdaudio_ext.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "shim.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* PCI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCI_TCSEL 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCI_PGCTL PCI_TCSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCI_CGCTL 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* PCI_PGCTL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCI_PGCTL_ADSPPGD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCI_PGCTL_LSRMD_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* PCI_CGCTL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCI_CGCTL_MISCBDCGE_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCI_CGCTL_ADSPDCGE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Legacy HDA registers and bits used - widths are variable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SOF_HDA_GCAP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SOF_HDA_GCTL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* accept unsol. response enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SOF_HDA_GCTL_UNSOL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SOF_HDA_LLCH 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SOF_HDA_INTCTL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SOF_HDA_INTSTS 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SOF_HDA_WAKESTS 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SOF_HDA_RIRBSTS 0x5d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* SOF_HDA_GCTL register bist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SOF_HDA_GCTL_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* SOF_HDA_INCTL regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SOF_HDA_INT_GLOBAL_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SOF_HDA_INT_CTRL_EN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SOF_HDA_INT_ALL_STREAM 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* SOF_HDA_INTSTS regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SOF_HDA_INTSTS_GIS BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SOF_HDA_MAX_CAPS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SOF_HDA_CAP_ID_OFF 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) SOF_HDA_CAP_ID_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SOF_HDA_CAP_NEXT_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SOF_HDA_GTS_CAP_ID 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SOF_HDA_ML_CAP_ID 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SOF_HDA_PP_CAP_ID 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SOF_HDA_REG_PP_PPCH 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SOF_HDA_REG_PP_PPCTL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SOF_HDA_REG_PP_PPSTS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SOF_HDA_PPCTL_PIE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SOF_HDA_PPCTL_GPROCEN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*Vendor Specific Registers*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SOF_HDA_VS_D0I3C 0x104A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* D0I3C Register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* DPIB entry size: 8 Bytes = 2 DWords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SOF_HDA_DPIB_ENTRY_SIZE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SOF_HDA_SPIB_CAP_ID 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SOF_HDA_DRSM_CAP_ID 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SOF_HDA_SPIB_BASE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SOF_HDA_SPIB_INTERVAL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SOF_HDA_SPIB_SPIB 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SOF_HDA_SPIB_MAXFIFO 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SOF_HDA_PPHC_BASE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SOF_HDA_PPHC_INTERVAL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SOF_HDA_PPLC_BASE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SOF_HDA_PPLC_MULTI 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SOF_HDA_PPLC_INTERVAL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SOF_HDA_DRSM_BASE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SOF_HDA_DRSM_INTERVAL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Descriptor error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* FIFO error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Buffer completion interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SOF_HDA_CL_DMA_SD_INT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SOF_HDA_CL_DMA_SD_INT_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Intel HD Audio Code Loader DMA Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SOF_HDA_ADSP_LOADER_BASE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SOF_HDA_ADSP_DPLBASE 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SOF_HDA_ADSP_DPUBASE 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Stream Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SOF_HDA_ADSP_REG_CL_SD_STS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* CL: Software Position Based FIFO Capability Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SOF_DSP_REG_CL_SPBFIFO \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (SOF_HDA_ADSP_LOADER_BASE + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Stream Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HDA_DSP_HDA_BAR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HDA_DSP_PP_BAR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HDA_DSP_SPIB_BAR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HDA_DSP_DRSM_BAR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HDA_DSP_BAR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define HDA_DSP_PANIC_OFFSET(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* SRAM window 0 FW "registers" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* FW and ROM share offset 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define HDA_DSP_STREAM_RESET_TIMEOUT 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * Timeout in us, for setting the stream RUN bit, during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * start/stop the stream. The timeout expires if new RUN bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * value cannot be read back within the specified time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define HDA_DSP_STREAM_RUN_TIMEOUT 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define HDA_DSP_SPIB_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define HDA_DSP_SPIB_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define HDA_DSP_STACK_DUMP_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* ROM status/error values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define HDA_DSP_ROM_STS_MASK GENMASK(23, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define HDA_DSP_ROM_INIT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define HDA_DSP_ROM_FW_FW_LOADED 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define HDA_DSP_ROM_FW_ENTERED 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define HDA_DSP_ROM_RFW_START 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define HDA_DSP_ROM_CSE_ERROR 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define HDA_DSP_ROM_IMR_TO_SMALL 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define HDA_DSP_ROM_IPC_FATAL_ERROR 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define HDA_DSP_ROM_L2_CACHE_ERROR 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define HDA_DSP_ROM_API_PTR_INVALID 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define HDA_DSP_ROM_BASEFW_INCOMPAT 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define HDA_DSP_IPC_PURGE_FW 0x01004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* various timeout values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define HDA_DSP_PU_TIMEOUT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define HDA_DSP_PD_TIMEOUT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define HDA_DSP_RESET_TIMEOUT_US 50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define HDA_DSP_BASEFW_TIMEOUT_US 3000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define HDA_DSP_INIT_TIMEOUT_US 500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define HDA_DSP_CTRL_RESET_TIMEOUT 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define HDA_DSP_REG_POLL_RETRY_COUNT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define HDA_DSP_ADSPIC_IPC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define HDA_DSP_ADSPIS_IPC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Intel HD Audio General DSP Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define HDA_DSP_GEN_BASE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define HDA_DSP_REG_ADSPIS2_SNDW BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define HDA_DSP_REG_SNDW_WAKE_STS 0x2C192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Intel HD Audio Inter-Processor Communication Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define HDA_DSP_IPC_BASE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Intel Vendor Specific Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define HDA_VS_INTEL_EM2 0x1030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define HDA_VS_INTEL_EM2_L1SEN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define HDA_VS_INTEL_LTRP_GB_MASK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* HIPCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define HDA_DSP_REG_HIPCI_BUSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* HIPCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define HDA_DSP_REG_HIPCIE_DONE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* HIPCCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define HDA_DSP_REG_HIPCCTL_DONE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* HIPCT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define HDA_DSP_REG_HIPCT_BUSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* HIPCTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define HDA_DSP_ADSPIC_CL_DMA 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define HDA_DSP_ADSPIS_CL_DMA 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Delay before scheduling D0i3 entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define BXT_D0I3_DELAY 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define FW_CL_STREAM_NUMBER 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define HDA_FW_BOOT_ATTEMPTS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* ADSPCS - Audio DSP Control & Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * Core Reset - asserted high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * CRST Mask for a given core mask pattern, cm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define HDA_DSP_ADSPCS_CRST_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Core run/stall - when set to '1' core is stalled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * CSTALL Mask for a given core mask pattern, cm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Set Power Active - when set to '1' turn cores on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * SPA Mask for a given core mask pattern, cm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define HDA_DSP_ADSPCS_SPA_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * Current Power Active - power status of cores, set by hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * CPA Mask for a given core mask pattern, cm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define HDA_DSP_ADSPCS_CPA_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * Mask for a given number of cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * nc = number of supported cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CNL_DSP_IPC_BASE 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* HIPCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* HIPCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define CNL_DSP_REG_HIPCIDA_DONE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* HIPCCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define CNL_DSP_REG_HIPCCTL_DONE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* HIPCT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* HIPCTDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define CNL_DSP_REG_HIPCTDA_DONE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* HIPCTDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* BDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define HDA_DSP_BDL_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define HDA_DSP_MAX_BDL_ENTRIES \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Number of DAIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define SOF_SKL_NUM_DAIS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SOF_SKL_NUM_DAIS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SOF_SKL_NUM_DAIS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Intel HD Audio SRAM Window 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define HDA_ADSP_SRAM0_BASE_SKL 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Firmware status window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Host Device Memory Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define APL_SSP_BASE_OFFSET 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define CNL_SSP_BASE_OFFSET 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Host Device Memory Size of a Single SSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SSP_DEV_MEM_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* SSP Count of the Platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define APL_SSP_COUNT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define CNL_SSP_COUNT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define ICL_SSP_COUNT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* SSP Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SSP_SSC1_OFFSET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define SSP_SET_SCLK_SLAVE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SSP_SET_SFRM_SLAVE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SSP_SET_SLAVE (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define HDA_IDISP_CODEC(x) ((x) & BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct sof_intel_dsp_bdl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) __le32 addr_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) __le32 addr_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) __le32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) __le32 ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) } __attribute((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define SOF_HDA_PLAYBACK_STREAMS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define SOF_HDA_CAPTURE_STREAMS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define SOF_HDA_PLAYBACK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SOF_HDA_CAPTURE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * Time in ms for opportunistic D0I3 entry delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * This has been deliberately chosen to be long to avoid race conditions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * Could be optimized in future.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define SOF_HDA_D0I3_WORK_DELAY_MS 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* HDA DSP D0 substate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) enum sof_hda_D0_substate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) SOF_HDA_DSP_PM_D0I0, /* default D0 substate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* represents DSP HDA controller frontend - i.e. host facing control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct sof_intel_hda_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int boot_iteration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct hda_bus hbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* hw config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) const struct sof_intel_dsp_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* trace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct hdac_ext_stream *dtrace_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* if position update IPC needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u32 no_ipc_position;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* the maximum number of streams (playback + capture) supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 stream_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* PM related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) bool l1_support_changed;/* during suspend, is L1SEN changed or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* DMIC device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct platform_device *dmic_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* delayed work to enter D0I3 opportunistically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct delayed_work d0i3_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* ACPI information stored between scan and probe steps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct sdw_intel_acpi_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* sdw context allocated by SoundWire driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct sdw_intel_ctx *sdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return &hda->hbus.core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return &hda->hbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct sof_intel_hda_stream {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct snd_sof_dev *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct hdac_ext_stream hda_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct sof_intel_stream stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int host_reserved; /* reserve host DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define hstream_to_sof_hda_stream(hstream) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) container_of(hstream, struct sof_intel_hda_stream, hda_stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define bus_to_sof_hda(bus) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) container_of(bus, struct sof_intel_hda_dev, hbus.core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define SOF_STREAM_SD_OFFSET(s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) + SOF_HDA_ADSP_LOADER_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * DSP Core services.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int hda_dsp_probe(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int hda_dsp_remove(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) unsigned int core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) unsigned int core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned int core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) unsigned int core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) const struct sof_dsp_power_state *target_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int hda_dsp_resume(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int hda_dsp_runtime_idle(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) void hda_ipc_dump(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) void hda_dsp_d0i3_work(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * DSP PCM Operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct snd_pcm_substream *substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct snd_pcm_substream *substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct sof_ipc_stream_params *ipc_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct snd_pcm_substream *substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct snd_pcm_substream *substream, int cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct snd_pcm_substream *substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * DSP Stream Operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int hda_dsp_stream_init(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) void hda_dsp_stream_free(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct hdac_ext_stream *stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct snd_dma_buffer *dmab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct snd_pcm_hw_params *params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct snd_dma_buffer *dmab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct snd_pcm_hw_params *params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct hdac_ext_stream *stream, int cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct snd_dma_buffer *dmab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct hdac_stream *stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct hdac_ext_stream *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct hdac_ext_stream *stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int enable, u32 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) void hda_ipc_msg_data(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) void *p, size_t sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int hda_ipc_pcm_params(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) const struct sof_ipc_pcm_params_reply *reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * Probe Compress Operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int hda_probe_compr_assign(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct snd_compr_stream *cstream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct snd_soc_dai *dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int hda_probe_compr_free(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct snd_compr_stream *cstream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct snd_soc_dai *dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int hda_probe_compr_set_params(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct snd_compr_stream *cstream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct snd_compr_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct snd_soc_dai *dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) int hda_probe_compr_trigger(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct snd_compr_stream *cstream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct snd_soc_dai *dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int hda_probe_compr_pointer(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct snd_compr_stream *cstream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct snd_compr_tstamp *tstamp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct snd_soc_dai *dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * DSP IPC Operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct snd_sof_ipc_msg *msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * DSP Code loader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* pre and post fw run ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * HDA Controller Operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * HDA bus operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * HDA Codec operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) void hda_codec_probe_bus(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) bool hda_codec_use_common_hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) void hda_codec_jack_check(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #endif /* CONFIG_SND_SOC_SOF_HDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int hda_codec_i915_init(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) int hda_codec_i915_exit(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) bool enable) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * Trace Control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int hda_dsp_trace_release(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * SoundWire support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) int hda_sdw_startup(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) void hda_sdw_process_wakeen(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static inline int hda_sdw_probe(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static inline int hda_sdw_startup(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static inline int hda_sdw_exit(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static inline bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static inline irqreturn_t hda_dsp_sdw_thread(int irq, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* common dai driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) extern struct snd_soc_dai_driver skl_dai[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * Platform Specific HW abstraction Ops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) extern const struct snd_sof_dsp_ops sof_apl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) extern const struct snd_sof_dsp_ops sof_cnl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) extern const struct snd_sof_dsp_ops sof_tgl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) extern const struct sof_intel_dsp_desc apl_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) extern const struct sof_intel_dsp_desc cnl_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) extern const struct sof_intel_dsp_desc skl_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) extern const struct sof_intel_dsp_desc icl_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) extern const struct sof_intel_dsp_desc tgl_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) extern const struct sof_intel_dsp_desc tglh_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) extern const struct sof_intel_dsp_desc ehl_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) extern const struct sof_intel_dsp_desc jsl_chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* machine driver select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) void hda_machine_select(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) void hda_set_mach_params(const struct snd_soc_acpi_mach *mach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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