^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright(c) 2018 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) // Rander Wang <rander.wang@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) // Keyon Jie <yang.jie@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Hardware interface for generic Intel audio DSP HDA IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/hdaudio_ext.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/hda_register.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/soundwire/sdw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/soundwire/sdw_intel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/intel-nhlt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/sof.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <sound/sof/xtensa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "../sof-audio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "../ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "hda.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <sound/soc-acpi-intel-match.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* platform specific devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "shim.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define EXCEPT_MAX_HDR_SIZE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HDA_EXT_ROM_STATUS_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * The default for SoundWire clock stop quirks is to power gate the IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * and do a Bus Reset, this will need to be modified when the DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * needs to remain in D0i3 so that the Master does not lose context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * and enumeration is not required on clock restart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int sdw_clock_stop_quirks = SDW_INTEL_CLK_STOP_BUS_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) module_param(sdw_clock_stop_quirks, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MODULE_PARM_DESC(sdw_clock_stop_quirks, "SOF SoundWire clock stop quirks");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int sdw_params_stream(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct sdw_intel_stream_params_data *params_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct snd_sof_dev *sdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct snd_soc_dai *d = params_data->dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct sof_ipc_dai_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct sof_ipc_reply reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int link_id = params_data->link_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int alh_stream_id = params_data->alh_stream_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 size = sizeof(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) memset(&config, 0, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) config.hdr.size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) config.hdr.cmd = SOF_IPC_GLB_DAI_MSG | SOF_IPC_DAI_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) config.type = SOF_DAI_INTEL_ALH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) config.dai_index = (link_id << 8) | (d->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) config.alh.stream_id = alh_stream_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* send message to DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ret = sof_ipc_tx_message(sdev->ipc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) config.hdr.cmd, &config, size, &reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) sizeof(reply));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "error: failed to set DAI hw_params for link %d dai->id %d ALH %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) link_id, d->id, alh_stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int sdw_free_stream(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct sdw_intel_stream_free_data *free_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct snd_sof_dev *sdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct snd_soc_dai *d = free_data->dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct sof_ipc_dai_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct sof_ipc_reply reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int link_id = free_data->link_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 size = sizeof(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) memset(&config, 0, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) config.hdr.size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) config.hdr.cmd = SOF_IPC_GLB_DAI_MSG | SOF_IPC_DAI_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) config.type = SOF_DAI_INTEL_ALH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) config.dai_index = (link_id << 8) | d->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) config.alh.stream_id = 0xFFFF; /* invalid value on purpose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* send message to DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret = sof_ipc_tx_message(sdev->ipc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) config.hdr.cmd, &config, size, &reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) sizeof(reply));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "error: failed to free stream for link %d dai->id %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) link_id, d->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct sdw_intel_ops sdw_callback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .params_stream = sdw_params_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .free_stream = sdw_free_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) sdw_intel_enable_irq(sdev->bar[HDA_DSP_BAR], enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int hda_sdw_acpi_scan(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct sof_intel_hda_dev *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) acpi_handle handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) handle = ACPI_HANDLE(sdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* save ACPI info for the probe step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) hdev = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ret = sdw_intel_acpi_scan(handle, &hdev->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int hda_sdw_probe(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct sof_intel_hda_dev *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct sdw_intel_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void *sdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) hdev = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) memset(&res, 0, sizeof(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) res.mmio_base = sdev->bar[HDA_DSP_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) res.irq = sdev->ipc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) res.handle = hdev->info.handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) res.parent = sdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) res.ops = &sdw_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) res.dev = sdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) res.clock_stop_quirks = sdw_clock_stop_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * ops and arg fields are not populated for now,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * they will be needed when the DAI callbacks are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* we could filter links here if needed, e.g for quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) res.count = hdev->info.count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) res.link_mask = hdev->info.link_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) sdw = sdw_intel_probe(&res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!sdw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_err(sdev->dev, "error: SoundWire probe failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* save context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) hdev->sdw = sdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int hda_sdw_startup(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct sof_intel_hda_dev *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) hdev = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!hdev->sdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return sdw_intel_startup(hdev->sdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int hda_sdw_exit(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct sof_intel_hda_dev *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) hdev = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) hda_sdw_int_enable(sdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (hdev->sdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) sdw_intel_exit(hdev->sdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) hdev->sdw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct sof_intel_hda_dev *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) bool ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) hdev = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!hdev->sdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* store status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* invalid message ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (irq_status == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* SDW message ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (irq_status & HDA_DSP_REG_ADSPIS2_SNDW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static irqreturn_t hda_dsp_sdw_thread(int irq, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return sdw_intel_thread(irq, context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct sof_intel_hda_dev *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) hdev = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (hdev->sdw &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) snd_sof_dsp_read(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) HDA_DSP_REG_SNDW_WAKE_STS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct sof_intel_hda_dev *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) hdev = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!hdev->sdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) sdw_intel_process_wakeen_event(hdev->sdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * Debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct hda_dsp_msg_code {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) const char *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static bool hda_use_msi = IS_ENABLED(CONFIG_PCI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) module_param_named(use_msi, hda_use_msi, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MODULE_PARM_DESC(use_msi, "SOF HDA use PCI MSI mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static char *hda_model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) module_param(hda_model, charp, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MODULE_PARM_DESC(hda_model, "Use the given HDA board model.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int hda_dmic_num = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) module_param_named(dmic_num, hda_dmic_num, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MODULE_PARM_DESC(dmic_num, "SOF HDA DMIC number");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static bool hda_codec_use_common_hdmi = IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) module_param_named(use_common_hdmi, hda_codec_use_common_hdmi, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MODULE_PARM_DESC(use_common_hdmi, "SOF HDA use common HDMI codec driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const struct hda_dsp_msg_code hda_dsp_rom_msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {HDA_DSP_ROM_FW_MANIFEST_LOADED, "status: manifest loaded"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {HDA_DSP_ROM_FW_FW_LOADED, "status: fw loaded"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {HDA_DSP_ROM_FW_ENTERED, "status: fw entered"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {HDA_DSP_ROM_CSE_ERROR, "error: cse error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void hda_dsp_get_status_skl(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) HDA_ADSP_FW_STATUS_SKL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (status == hda_dsp_rom_msg[i].code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev_err(sdev->dev, "%s - code %8.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) hda_dsp_rom_msg[i].msg, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* not for us, must be generic sof message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static void hda_dsp_get_status(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) HDA_DSP_SRAM_REG_ROM_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (status == hda_dsp_rom_msg[i].code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_err(sdev->dev, "%s - code %8.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) hda_dsp_rom_msg[i].msg, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* not for us, must be generic sof message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static void hda_dsp_get_registers(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct sof_ipc_dsp_oops_xtensa *xoops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct sof_ipc_panic_info *panic_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 *stack, size_t stack_words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 offset = sdev->dsp_oops_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* first read registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* note: variable AR register array is not read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* then get panic info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) xoops->arch_hdr.totalsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) offset += xoops->arch_hdr.totalsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) sof_block_read(sdev, sdev->mmio_bar, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) panic_info, sizeof(*panic_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* then get the stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) offset += sizeof(*panic_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) sof_block_read(sdev, sdev->mmio_bar, offset, stack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) stack_words * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct sof_ipc_dsp_oops_xtensa xoops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct sof_ipc_panic_info panic_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 stack[HDA_DSP_STACK_DUMP_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 status, panic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* try APL specific status message types first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) hda_dsp_get_status_skl(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* now try generic SOF status messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) HDA_ADSP_ERROR_CODE_SKL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /*TODO: Check: there is no define in spec, but it is used in the code*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) HDA_ADSP_ERROR_CODE_SKL + 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (sdev->fw_state == SOF_FW_BOOT_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) HDA_DSP_STACK_DUMP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) stack, HDA_DSP_STACK_DUMP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_err(sdev->dev, "error: status = 0x%8.8x panic = 0x%8.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) status, panic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) hda_dsp_get_status_skl(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* dump the first 8 dwords representing the extended ROM status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) char msg[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) for (i = 0; i < HDA_EXT_ROM_STATUS_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) value = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_ROM_STATUS + i * 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) len += snprintf(msg + len, sizeof(msg) - len, " 0x%x", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) sof_dev_dbg_or_err(sdev->dev, hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "extended rom status: %s", msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct sof_ipc_dsp_oops_xtensa xoops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct sof_ipc_panic_info panic_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u32 stack[HDA_DSP_STACK_DUMP_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u32 status, panic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* try APL specific status message types first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) hda_dsp_get_status(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* now try generic SOF status messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) HDA_DSP_SRAM_REG_FW_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (sdev->fw_state == SOF_FW_BOOT_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) HDA_DSP_STACK_DUMP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) stack, HDA_DSP_STACK_DUMP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) sof_dev_dbg_or_err(sdev->dev, hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) "status = 0x%8.8x panic = 0x%8.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) status, panic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) hda_dsp_dump_ext_rom_status(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) hda_dsp_get_status(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) void hda_ipc_irq_dump(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct hdac_bus *bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u32 adspis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u32 intsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u32 intctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u32 ppsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u8 rirbsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* read key IRQ stats and config registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) rirbsts = snd_hdac_chip_readb(bus, RIRBSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) "error: hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) intsts, intctl, rirbsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) "error: dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ppsts, adspis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) void hda_ipc_dump(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u32 hipcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u32 hipct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 hipcctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) hda_ipc_irq_dump(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* read IPC status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* dump the IPC regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* TODO: parse the raw msg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) "error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) hipcie, hipct, hipcctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int hda_init(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct hda_bus *hbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct hdac_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct pci_dev *pci = to_pci_dev(sdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) hbus = sof_to_hbus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* HDA bus init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) sof_hda_bus_init(bus, &pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) bus->use_posbuf = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) bus->bdl_pos_adj = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) bus->sync_write = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) mutex_init(&hbus->prepare_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) hbus->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) hbus->mixer_assigned = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) hbus->modelname = hda_model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* initialise hdac bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) bus->addr = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #if IS_ENABLED(CONFIG_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) bus->remap_addr = pci_ioremap_bar(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (!bus->remap_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dev_err(bus->dev, "error: ioremap error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* HDA base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* init i915 and HDMI codecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret = hda_codec_i915_init(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev_warn(sdev->dev, "init of i915 and HDMI codec failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* get controller capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret = hda_dsp_ctrl_get_caps(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dev_err(sdev->dev, "error: get caps error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int check_nhlt_dmic(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct nhlt_acpi_table *nhlt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int dmic_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) nhlt = intel_nhlt_init(sdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (nhlt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dmic_num = intel_nhlt_get_dmic_geo(sdev->dev, nhlt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) intel_nhlt_free(nhlt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (dmic_num >= 1 && dmic_num <= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return dmic_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static const char *fixup_tplg_name(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) const char *sof_tplg_filename,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) const char *idisp_str,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) const char *dmic_str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) const char *tplg_filename = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) char *filename;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) char *split_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (!filename)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* this assumes a .tplg extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) split_ext = strsep(&filename, ".");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (split_ext) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) "%s%s%s.tplg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) split_ext, idisp_str, dmic_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (!tplg_filename)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return tplg_filename;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int hda_init_caps(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct hdac_bus *bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct snd_sof_pdata *pdata = sdev->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct hdac_ext_link *hlink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct sof_intel_hda_dev *hdev = pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u32 link_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) device_disable_async_suspend(bus->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* check if dsp is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (bus->ppcap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* Init HDA controller after i915 init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ret = hda_dsp_ctrl_init_chip(sdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) dev_err(bus->dev, "error: init chip failed with ret: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* scan SoundWire capabilities exposed by DSDT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = hda_sdw_acpi_scan(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) goto skip_soundwire;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) link_mask = hdev->info.link_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (!link_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dev_dbg(sdev->dev, "skipping SoundWire, no links enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) goto skip_soundwire;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * probe/allocate SoundWire resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * The hardware configuration takes place in hda_sdw_startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * after power rails are enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * It's entirely possible to have a mix of I2S/DMIC/SoundWire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * devices, so we allocate the resources in all cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ret = hda_sdw_probe(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dev_err(sdev->dev, "error: SoundWire probe error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) skip_soundwire:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (bus->mlcap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) snd_hdac_ext_bus_get_ml_capabilities(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* create codec instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) hda_codec_probe_bus(sdev, hda_codec_use_common_hdmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (!HDA_IDISP_CODEC(bus->codec_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) hda_codec_i915_display_power(sdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * we are done probing so decrement link counts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) list_for_each_entry(hlink, &bus->hlink_list, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) snd_hdac_ext_bus_link_put(bus, hlink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static const struct sof_intel_dsp_desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) *get_chip_info(struct snd_sof_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) const struct sof_dev_desc *desc = pdata->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) const struct sof_intel_dsp_desc *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) chip_info = desc->chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static irqreturn_t hda_dsp_interrupt_handler(int irq, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct snd_sof_dev *sdev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * Get global interrupt status. It includes all hardware interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * sources in the Intel HD Audio controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) SOF_HDA_INTSTS_GIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* disable GIE interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) SOF_HDA_INTCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) SOF_HDA_INT_GLOBAL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static irqreturn_t hda_dsp_interrupt_thread(int irq, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct snd_sof_dev *sdev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* deal with streams and controller first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (hda_dsp_check_stream_irq(sdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) hda_dsp_stream_threaded_handler(irq, sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (hda_dsp_check_ipc_irq(sdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) sof_ops(sdev)->irq_thread(irq, sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (hda_dsp_check_sdw_irq(sdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) hda_dsp_sdw_thread(irq, hdev->sdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (hda_sdw_check_wakeen_irq(sdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) hda_sdw_process_wakeen(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* enable GIE interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) SOF_HDA_INTCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) SOF_HDA_INT_GLOBAL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) SOF_HDA_INT_GLOBAL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) int hda_dsp_probe(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct pci_dev *pci = to_pci_dev(sdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct sof_intel_hda_dev *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct hdac_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) const struct sof_intel_dsp_desc *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * detect DSP by checking class/subclass/prog-id information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * class=04 subclass 03 prog-if 00: no DSP, legacy driver is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * class=04 subclass 01 prog-if 00: DSP is present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * (and may be required e.g. for DMIC or SSP support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * class=04 subclass 03 prog-if 80: either of DSP or legacy mode works
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (pci->class == 0x040300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dev_err(sdev->dev, "error: the DSP is not enabled on this platform, aborting probe\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) } else if (pci->class != 0x040100 && pci->class != 0x040380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) dev_err(sdev->dev, "error: unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n", pci->class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n", pci->class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) chip = get_chip_info(sdev->pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (!chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dev_err(sdev->dev, "error: no such device supported, chip id:%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) pci->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) hdev = devm_kzalloc(sdev->dev, sizeof(*hdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (!hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) sdev->pdata->hw_pdata = hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) hdev->desc = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) hdev->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PLATFORM_DEVID_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (IS_ERR(hdev->dmic_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) dev_err(sdev->dev, "error: failed to create DMIC device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return PTR_ERR(hdev->dmic_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * use position update IPC if either it is forced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * or we don't have other choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) hdev->no_ipc_position = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) hdev->no_ipc_position = sof_ops(sdev)->pcm_pointer ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* set up HDA base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ret = hda_init(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) goto hdac_bus_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* DSP base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #if IS_ENABLED(CONFIG_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (!sdev->bar[HDA_DSP_BAR]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_err(sdev->dev, "error: ioremap error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) goto hdac_bus_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) sdev->mmio_bar = HDA_DSP_BAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) sdev->mailbox_bar = HDA_DSP_BAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* allow 64bit DMA address if supported by H/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(64))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dev_dbg(sdev->dev, "DMA mask is 64 bit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dev_dbg(sdev->dev, "DMA mask is 32 bit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* init streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ret = hda_dsp_stream_init(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev_err(sdev->dev, "error: failed to init streams\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * not all errors are due to memory issues, but trying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * to free everything does not harm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) goto free_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * register our IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * let's try to enable msi firstly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * if it fails, use legacy interrupt mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * TODO: support msi multiple vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (hda_use_msi && pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) dev_info(sdev->dev, "use msi interrupt mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) sdev->ipc_irq = pci_irq_vector(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* initialised to "false" by kzalloc() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) sdev->msi_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (!sdev->msi_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dev_info(sdev->dev, "use legacy interrupt mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * in IO-APIC mode, hda->irq and ipc_irq are using the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * irq number of pci->irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) sdev->ipc_irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_interrupt_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) hda_dsp_interrupt_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) IRQF_SHARED, "AudioDSP", sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) sdev->ipc_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) goto free_irq_vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) synchronize_irq(pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * clear TCSEL to clear playback on some HD Audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * codecs. PCI TCSEL is defined in the Intel manuals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* init HDA capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) ret = hda_init_caps(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) goto free_ipc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* enable ppcap interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) hda_dsp_ctrl_ppcap_enable(sdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) hda_dsp_ctrl_ppcap_int_enable(sdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* set default mailbox offset for FW ready message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) INIT_DELAYED_WORK(&hdev->d0i3_work, hda_dsp_d0i3_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) free_ipc_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) free_irq(sdev->ipc_irq, sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) free_irq_vector:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (sdev->msi_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) pci_free_irq_vectors(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) free_streams:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) hda_dsp_stream_free(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* dsp_unmap: not currently used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) iounmap(sdev->bar[HDA_DSP_BAR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) hdac_bus_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) platform_device_unregister(hdev->dmic_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) iounmap(bus->remap_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) hda_codec_i915_exit(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) int hda_dsp_remove(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct hdac_bus *bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct pci_dev *pci = to_pci_dev(sdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) const struct sof_intel_dsp_desc *chip = hda->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* cancel any attempt for DSP D0I3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) cancel_delayed_work_sync(&hda->d0i3_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* codec removal, invoke bus_device_remove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) snd_hdac_ext_bus_device_remove(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) hda_sdw_exit(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!IS_ERR_OR_NULL(hda->dmic_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) platform_device_unregister(hda->dmic_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /* disable DSP IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) SOF_HDA_PPCTL_PIE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* disable CIE and GIE interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* disable cores */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* disable DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) SOF_HDA_PPCTL_GPROCEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) free_irq(sdev->ipc_irq, sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (sdev->msi_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) pci_free_irq_vectors(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) hda_dsp_stream_free(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) snd_hdac_link_free_all(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) iounmap(sdev->bar[HDA_DSP_BAR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) iounmap(bus->remap_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) snd_hdac_ext_bus_exit(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) hda_codec_i915_exit(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static int hda_generic_machine_select(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct hdac_bus *bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct snd_soc_acpi_mach_params *mach_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct snd_soc_acpi_mach *hda_mach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct snd_sof_pdata *pdata = sdev->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) const char *tplg_filename;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) const char *idisp_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) const char *dmic_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) int dmic_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) int codec_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* codec detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (!bus->codec_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) dev_info(bus->dev, "no hda codecs found!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) dev_info(bus->dev, "hda codecs found, mask %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) bus->codec_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) for (i = 0; i < HDA_MAX_CODECS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (bus->codec_mask & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) codec_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * If no machine driver is found, then:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * generic hda machine driver can handle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * - one HDMI codec, and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * - one external HDAudio codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (!pdata->machine && codec_num <= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) hda_mach = snd_soc_acpi_intel_hda_machines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* topology: use the info from hda_machines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) pdata->tplg_filename =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) hda_mach->sof_tplg_filename;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) dev_info(bus->dev, "using HDA machine driver %s now\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) hda_mach->drv_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (codec_num == 1 && HDA_IDISP_CODEC(bus->codec_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) idisp_str = "-idisp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) idisp_str = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* first check NHLT for DMICs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) dmic_num = check_nhlt_dmic(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* allow for module parameter override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (hda_dmic_num != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) dmic_num = hda_dmic_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) switch (dmic_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) dmic_str = "-1ch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dmic_str = "-2ch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) dmic_str = "-3ch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) dmic_str = "-4ch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) dmic_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) dmic_str = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) tplg_filename = pdata->tplg_filename;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) tplg_filename = fixup_tplg_name(sdev, tplg_filename,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) idisp_str, dmic_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (!tplg_filename)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) dev_info(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) "DMICs detected in NHLT tables: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) dmic_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) pdata->machine = hda_mach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) pdata->tplg_filename = tplg_filename;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* used by hda machine driver to create dai links */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (pdata->machine) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) mach_params = (struct snd_soc_acpi_mach_params *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) &pdata->machine->mach_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) mach_params->codec_mask = bus->codec_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) mach_params->common_hdmi_codec_drv = hda_codec_use_common_hdmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) mach_params->dmic_num = dmic_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static int hda_generic_machine_select(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* Check if all Slaves defined on the link can be found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static bool link_slaves_found(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) const struct snd_soc_acpi_link_adr *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct sdw_intel_ctx *sdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) struct hdac_bus *bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct sdw_intel_slave_id *ids = sdw->ids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) int num_slaves = sdw->num_slaves;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) unsigned int part_id, link_id, unique_id, mfg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) for (i = 0; i < link->num_adr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) u64 adr = link->adr_d[i].adr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) mfg_id = SDW_MFG_ID(adr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) part_id = SDW_PART_ID(adr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) link_id = SDW_DISCO_LINK_ID(adr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) for (j = 0; j < num_slaves; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (ids[j].link_id != link_id ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) ids[j].id.part_id != part_id ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ids[j].id.mfg_id != mfg_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * we have to check unique id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * if there is more than one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * Slave on the link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) unique_id = SDW_UNIQUE_ID(adr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (link->num_adr == 1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ids[j].id.unique_id == SDW_IGNORED_UNIQUE_ID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) ids[j].id.unique_id == unique_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) dev_dbg(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) "found %x at link %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) part_id, link_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (j == num_slaves) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) dev_dbg(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) "Slave %x not found\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) part_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) static int hda_sdw_machine_select(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct snd_sof_pdata *pdata = sdev->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) const struct snd_soc_acpi_link_adr *link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct hdac_bus *bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct snd_soc_acpi_mach *mach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct sof_intel_hda_dev *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) u32 link_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) hdev = pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) link_mask = hdev->info.link_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * Select SoundWire machine driver if needed using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * alternate tables. This case deals with SoundWire-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * machines, for mixed cases with I2C/I2S the detection relies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) * on the HID list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (link_mask && !pdata->machine) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) for (mach = pdata->desc->alt_machines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) mach && mach->link_mask; mach++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * On some platforms such as Up Extreme all links
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * are enabled but only one link can be used by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * external codec. Instead of exact match of two masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * first check whether link_mask of mach is subset of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * link_mask supported by hw and then go on searching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * link_adr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (~link_mask & mach->link_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /* No need to match adr if there is no links defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (!mach->links)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) link = mach->links;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) for (i = 0; i < hdev->info.count && link->num_adr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) i++, link++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * Try next machine if any expected Slaves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * are not found on this link.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (!link_slaves_found(sdev, link, hdev->sdw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* Found if all Slaves are checked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (i == hdev->info.count || !link->num_adr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (mach && mach->link_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) dev_dbg(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) "SoundWire machine driver %s topology %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) mach->drv_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) mach->sof_tplg_filename);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) pdata->machine = mach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) mach->mach_params.links = mach->links;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) mach->mach_params.link_mask = mach->link_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) mach->mach_params.platform = dev_name(sdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) pdata->fw_filename = mach->sof_fw_filename;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) pdata->tplg_filename = mach->sof_tplg_filename;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) dev_info(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) "No SoundWire machine driver found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static int hda_sdw_machine_select(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) void hda_set_mach_params(const struct snd_soc_acpi_mach *mach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct snd_soc_acpi_mach_params *mach_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) mach_params = (struct snd_soc_acpi_mach_params *)&mach->mach_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) mach_params->platform = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) void hda_machine_select(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) struct snd_sof_pdata *sof_pdata = sdev->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) const struct sof_dev_desc *desc = sof_pdata->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) struct snd_soc_acpi_mach *mach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) mach = snd_soc_acpi_find_machine(desc->machines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (mach) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * If tplg file name is overridden, use it instead of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * the one set in mach table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (!sof_pdata->tplg_filename)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) sof_pdata->tplg_filename = mach->sof_tplg_filename;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) sof_pdata->machine = mach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (mach->link_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) mach->mach_params.links = mach->links;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) mach->mach_params.link_mask = mach->link_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) * If I2S fails, try SoundWire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) hda_sdw_machine_select(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * Choose HDA generic machine driver if mach is NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * Otherwise, set certain mach params.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) hda_generic_machine_select(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (!sof_pdata->machine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) MODULE_LICENSE("Dual BSD/GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC_I915);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) MODULE_IMPORT_NS(SOUNDWIRE_INTEL_INIT);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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