^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright(c) 2018 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) // Rander Wang <rander.wang@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) // Keyon Jie <yang.jie@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Hardware interface for HDA DSP code loader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/hdaudio_ext.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/hda_register.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/sof.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "../ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "hda.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HDA_FW_BOOT_ATTEMPTS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HDA_CL_STREAM_FORMAT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static struct hdac_ext_stream *cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned int size, struct snd_dma_buffer *dmab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct hdac_ext_stream *dsp_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct hdac_stream *hstream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct pci_dev *pci = to_pci_dev(sdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) dsp_stream = hda_dsp_stream_get(sdev, direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (!dsp_stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) dev_err(sdev->dev, "error: no stream available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) hstream = &dsp_stream->hstream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) hstream->substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* allocate DMA buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, &pci->dev, size, dmab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) dev_err(sdev->dev, "error: memory alloc failed: %x\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) hstream->period_bytes = 0;/* initialize period_bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) hstream->format_val = format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) hstream->bufsize = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (direction == SNDRV_PCM_STREAM_CAPTURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ret = hda_dsp_iccmax_stream_hw_params(sdev, dsp_stream, dmab, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dev_err(sdev->dev, "error: iccmax stream prepare failed: %x\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ret = hda_dsp_stream_hw_params(sdev, dsp_stream, dmab, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) dev_err(sdev->dev, "error: hdac prepare failed: %x\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) hda_dsp_stream_spib_config(sdev, dsp_stream, HDA_DSP_SPIB_ENABLE, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return dsp_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) snd_dma_free_pages(dmab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) out_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) hda_dsp_stream_put(sdev, direction, hstream->stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * first boot sequence has some extra steps. core 0 waits for power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * status on core 1, so power up core 1 also momentarily, keep it in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * reset/stall and then turn it off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const struct sof_intel_dsp_desc *chip = hda->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* step 1: power up corex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ret = hda_dsp_core_power_up(sdev, chip->host_managed_cores_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* DSP is powered up, set all SSPs to slave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) for (i = 0; i < chip->ssp_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) chip->ssp_base_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) + i * SSP_DEV_MEM_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) + SSP_SSC1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SSP_SET_SLAVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) SSP_SET_SLAVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* step 2: purge FW request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) chip->ipc_req_mask | (HDA_DSP_IPC_PURGE_FW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ((stream_tag - 1) << 9)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* step 3: unset core 0 reset state & unstall/run core 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = hda_dsp_core_run(sdev, BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "error: dsp core start failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* step 4: wait for IPC DONE bit from ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) chip->ipc_ack, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ((status & chip->ipc_ack_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) == chip->ipc_ack_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) HDA_DSP_REG_POLL_INTERVAL_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) HDA_DSP_INIT_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "error: %s: timeout for HIPCIE done\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* set DONE bit to clear the reply IPC message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) chip->ipc_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) chip->ipc_ack_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) chip->ipc_ack_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* step 5: power down corex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = hda_dsp_core_power_down(sdev, chip->host_managed_cores_mask & ~(BIT(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "error: dsp core x power down failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* step 6: enable IPC interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) hda_dsp_ipc_int_enable(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* step 7: wait for ROM init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) HDA_DSP_SRAM_REG_ROM_STATUS, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ((status & HDA_DSP_ROM_STS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) == HDA_DSP_ROM_INIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) HDA_DSP_REG_POLL_INTERVAL_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) chip->rom_init_timeout *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) USEC_PER_MSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int cl_trigger(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct hdac_ext_stream *stream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct hdac_stream *hstream = &stream->hstream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* code loader is special case that reuses stream ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 1 << hstream->index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 1 << hstream->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) sd_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) SOF_HDA_SD_CTL_DMA_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) SOF_HDA_CL_DMA_SD_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) SOF_HDA_SD_CTL_DMA_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) SOF_HDA_CL_DMA_SD_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) hstream->running = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return hda_dsp_stream_trigger(sdev, stream, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct hdac_ext_stream *stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct hdac_stream *hstream = &stream->hstream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret = hda_dsp_stream_spib_config(sdev, stream, HDA_DSP_SPIB_DISABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) SOF_HDA_SD_CTL_DMA_START, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) hda_dsp_stream_put(sdev, hstream->direction, hstream->stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) hstream->running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) hstream->substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* reset BDL address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) snd_dma_free_pages(dmab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dmab->area = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) hstream->bufsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) hstream->format_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int ret, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_err(sdev->dev, "error: DMA trigger start failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) HDA_DSP_SRAM_REG_ROM_STATUS, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ((reg & HDA_DSP_ROM_STS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) == HDA_DSP_ROM_FW_ENTERED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) HDA_DSP_REG_POLL_INTERVAL_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) HDA_DSP_BASEFW_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * even in case of errors we still need to stop the DMAs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * but we return the initial error should the DMA stop also fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_err(sdev->dev, "error: DMA trigger stop failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) status = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct snd_sof_pdata *plat_data = sdev->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct hdac_ext_stream *iccmax_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct hdac_bus *bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct firmware stripped_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int ret, ret1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u8 original_gb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* save the original LTRP guardband value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) original_gb = snd_hdac_chip_readb(bus, VS_LTRP) & HDA_VS_INTEL_LTRP_GB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (plat_data->fw->size <= plat_data->fw_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* prepare capture stream for ICCMAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) iccmax_stream = cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, stripped_firmware.size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) &sdev->dmab_bdl, SNDRV_PCM_STREAM_CAPTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (IS_ERR(iccmax_stream)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dev_err(sdev->dev, "error: dma prepare for ICCMAX stream failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return PTR_ERR(iccmax_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = hda_dsp_cl_boot_firmware(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * Perform iccmax stream cleanup. This should be done even if firmware loading fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * If the cleanup also fails, we return the initial error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret1 = cl_cleanup(sdev, &sdev->dmab_bdl, iccmax_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (ret1 < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_err(sdev->dev, "error: ICCMAX stream cleanup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* set return value to indicate cleanup failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = ret1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* restore the original guardband value after FW boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) snd_hdac_chip_updateb(bus, VS_LTRP, HDA_VS_INTEL_LTRP_GB_MASK, original_gb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct snd_sof_pdata *plat_data = sdev->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) const struct sof_dev_desc *desc = plat_data->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) const struct sof_intel_dsp_desc *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct hdac_ext_stream *stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct firmware stripped_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int ret, ret1, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) chip_info = desc->chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (plat_data->fw->size <= plat_data->fw_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) stripped_firmware.data = plat_data->fw->data + plat_data->fw_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* init for booting wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) init_waitqueue_head(&sdev->boot_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* prepare DMA for code loader stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) stream = cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, stripped_firmware.size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) &sdev->dmab, SNDRV_PCM_STREAM_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (IS_ERR(stream)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dev_err(sdev->dev, "error: dma prepare for fw loading failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return PTR_ERR(stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) memcpy(sdev->dmab.area, stripped_firmware.data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) stripped_firmware.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* try ROM init a few times before giving up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) for (i = 0; i < HDA_FW_BOOT_ATTEMPTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev_dbg(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "Attempting iteration %d of Core En/ROM load...\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) hda->boot_iteration = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ret = cl_dsp_init(sdev, stream->hstream.stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* don't retry anymore if successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (i == HDA_FW_BOOT_ATTEMPTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) i, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev_err(sdev->dev, "ROM error=0x%x: FW status=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) snd_sof_dsp_read(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) HDA_DSP_SRAM_REG_ROM_ERROR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) snd_sof_dsp_read(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) HDA_DSP_SRAM_REG_ROM_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * When a SoundWire link is in clock stop state, a Slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * device may trigger in-band wakes for events such as jack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * insertion or acoustic event detection. This event will lead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * to a WAKEEN interrupt, handled by the PCI device and routed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * to PME if the PCI device is in D3. The resume function in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * audio PCI driver will be invoked by ACPI for PME event and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * initialize the device and process WAKEEN interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * The WAKEEN interrupt should be processed ASAP to prevent an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * interrupt flood, otherwise other interrupts, such IPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * cannot work normally. The WAKEEN is handled after the ROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * is initialized successfully, which ensures power rails are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * enabled before accessing the SoundWire SHIM registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (!sdev->first_boot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) hda_sdw_process_wakeen(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * at this point DSP ROM has been initialized and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * should be ready for code loading and firmware boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = cl_copy_fw(sdev, stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_dbg(sdev->dev, "Firmware download successful, booting...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_err(sdev->dev, "error: load fw failed ret: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Perform codeloader stream cleanup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * This should be done even if firmware loading fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * If the cleanup also fails, we return the initial error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret1 = cl_cleanup(sdev, &sdev->dmab, stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (ret1 < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* set return value to indicate cleanup failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret = ret1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * return primary core id if both fw copy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * and stream clean up are successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return chip_info->init_core_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* dump dsp registers and disable DSP upon error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* disable DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) SOF_HDA_REG_PP_PPCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) SOF_HDA_PPCTL_GPROCEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* pre fw run operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* disable clock gating and power gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return hda_dsp_ctrl_clock_power_gating(sdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* post fw run operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int hda_dsp_post_fw_run(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (sdev->first_boot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ret = hda_sdw_startup(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) "error: could not startup SoundWire links\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) hda_sdw_int_enable(sdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* re-enable clock gating and power gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return hda_dsp_ctrl_clock_power_gating(sdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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