Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This file is provided under a dual BSD/GPLv2 license.  When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright(c) 2019 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Author: Keyon Jie <yang.jie@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __SOF_INTEL_HDA_IPC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __SOF_INTEL_HDA_IPC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * Primary register, mapped to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * - DIPCTDR (HIPCIDR) in sideband IPC (cAVS 1.8+)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * - DIPCT in cAVS 1.5 IPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * Secondary register, mapped to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * - DIPCTDD (HIPCIDD) in sideband IPC (cAVS 1.8+)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * - DIPCTE in cAVS 1.5 IPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Common bits in primary register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Reserved for doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HDA_IPC_RSVD_31		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Target, 0 - normal message, 1 - compact message(cAVS compatible) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HDA_IPC_MSG_COMPACT	BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Direction, 0 - request, 1 - response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HDA_IPC_RSP		BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HDA_IPC_TYPE_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HDA_IPC_TYPE_MASK	GENMASK(28, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HDA_IPC_TYPE(x)		((x) << HDA_IPC_TYPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HDA_IPC_PM_GATE		HDA_IPC_TYPE(0x8U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Command specific payload bits in secondary register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Disable DMA tracing (0 - keep tracing, 1 - to disable DMA trace) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HDA_PM_NO_DMA_TRACE	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Prevent clock gating (0 - cg allowed, 1 - DSP clock always on) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HDA_PM_PCG		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Prevent power gating (0 - deep power state transitions allowed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HDA_PM_PPG		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Indicates whether streaming is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HDA_PM_PG_STREAMING	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HDA_PM_PG_RSVD		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) irqreturn_t cnl_ipc_irq_thread(int irq, void *context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void cnl_ipc_dump(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #endif