^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright(c) 2018 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) // Rander Wang <rander.wang@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) // Keyon Jie <yang.jie@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Hardware interface for generic Intel audio DSP HDA IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "../ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "hda.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static void hda_dsp_ipc_host_done(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * tell DSP cmd is done - clear busy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * interrupt and send reply msg to dsp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) HDA_DSP_REG_HIPCT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) HDA_DSP_REG_HIPCT_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) HDA_DSP_REG_HIPCT_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* unmask BUSY interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) HDA_DSP_REG_HIPCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) HDA_DSP_REG_HIPCCTL_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) HDA_DSP_REG_HIPCCTL_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void hda_dsp_ipc_dsp_done(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * set DONE bit - tell DSP we have received the reply msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * from DSP, and processed it, don't send more reply to host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) HDA_DSP_REG_HIPCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) HDA_DSP_REG_HIPCIE_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) HDA_DSP_REG_HIPCIE_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* unmask Done interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) HDA_DSP_REG_HIPCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) HDA_DSP_REG_HIPCCTL_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) HDA_DSP_REG_HIPCCTL_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* send IPC message to DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) msg->msg_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) snd_sof_dsp_write(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) HDA_DSP_REG_HIPCI_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct snd_sof_ipc_msg *msg = sdev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct sof_ipc_reply reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct sof_ipc_cmd_hdr *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Sometimes, there is unexpected reply ipc arriving. The reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * ipc belongs to none of the ipcs sent from driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * In this case, the driver must ignore the ipc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (!msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) hdr = msg->msg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (hdr->cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) hdr->cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * memory windows are powered off before sending IPC reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * so we can't read the mailbox for CTX_SAVE and PM_GATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * replies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) reply.error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) reply.hdr.cmd = SOF_IPC_GLB_REPLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) reply.hdr.size = sizeof(reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) memcpy(msg->reply_data, &reply, sizeof(reply));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* get IPC reply from DSP in the mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) sof_mailbox_read(sdev, sdev->host_box.offset, &reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) sizeof(reply));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (reply.error < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) memcpy(msg->reply_data, &reply, sizeof(reply));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret = reply.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* reply correct size ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (reply.hdr.size != msg->reply_size &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* getter payload is never known upfront */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ((reply.hdr.cmd & SOF_GLB_TYPE_MASK) != SOF_IPC_GLB_PROBE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) msg->reply_size, reply.hdr.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* read the message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (msg->reply_size > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) sof_mailbox_read(sdev, sdev->host_box.offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) msg->reply_data, msg->reply_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) msg->reply_error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* IPC handler thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct snd_sof_dev *sdev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 hipci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 hipcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 hipct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 hipcte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 msg_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool ipc_irq = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* read IPC status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) HDA_DSP_REG_HIPCIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* is this a reply message from the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (hipcie & HDA_DSP_REG_HIPCIE_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) msg = hipci & HDA_DSP_REG_HIPCI_MSG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) msg_ext = hipcie & HDA_DSP_REG_HIPCIE_MSG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev_vdbg(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "ipc: firmware response, msg:0x%x, msg_ext:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) msg, msg_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* mask Done interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) HDA_DSP_REG_HIPCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) HDA_DSP_REG_HIPCCTL_DONE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Make sure the interrupt thread cannot be preempted between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * waking up the sender and re-enabling the interrupt. Also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * protect against a theoretical race with sof_ipc_tx_message():
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * if the DSP is fast enough to receive an IPC message, reply to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * it, and the host interrupt processing calls this function on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * a different core from the one, where the sending is taking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * place, the message might not yet be marked as expecting a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * reply.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) spin_lock_irq(&sdev->ipc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* handle immediate reply from DSP core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) hda_dsp_ipc_get_reply(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) snd_sof_ipc_reply(sdev, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* set the done bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) hda_dsp_ipc_dsp_done(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) spin_unlock_irq(&sdev->ipc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ipc_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* is this a new message from DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (hipct & HDA_DSP_REG_HIPCT_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) msg = hipct & HDA_DSP_REG_HIPCT_MSG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) msg_ext = hipcte & HDA_DSP_REG_HIPCTE_MSG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_vdbg(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "ipc: firmware initiated, msg:0x%x, msg_ext:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) msg, msg_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* mask BUSY interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) HDA_DSP_REG_HIPCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) HDA_DSP_REG_HIPCCTL_BUSY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* handle messages from DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if ((hipct & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* this is a PANIC message !! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* normal message - process normally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) snd_sof_ipc_msgs_rx(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) hda_dsp_ipc_host_done(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ipc_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (!ipc_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * This interrupt is not shared so no need to return IRQ_NONE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dev_dbg_ratelimited(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "nothing to do in IPC IRQ thread\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Check if an IPC IRQ occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) bool ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* store status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_vdbg(sdev->dev, "irq handler: irq_status:0x%x\n", irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* invalid message ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (irq_status == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* IPC message ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (irq_status & HDA_DSP_ADSPIS_IPC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return HDA_DSP_MBOX_UPLINK_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return SRAM_WINDOW_OFFSET(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) void hda_ipc_msg_data(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) void *p, size_t sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (!substream || !sdev->stream_box.size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) sof_mailbox_read(sdev, sdev->dsp_box.offset, p, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct hdac_stream *hstream = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct sof_intel_hda_stream *hda_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) hda_stream = container_of(hstream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct sof_intel_hda_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) hda_stream.hstream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* The stream might already be closed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (hstream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) sof_mailbox_read(sdev, hda_stream->stream.posn_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) p, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int hda_ipc_pcm_params(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) const struct sof_ipc_pcm_params_reply *reply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct hdac_stream *hstream = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct sof_intel_hda_stream *hda_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* validate offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) size_t posn_offset = reply->posn_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) hda_stream = container_of(hstream, struct sof_intel_hda_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) hda_stream.hstream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* check for unaligned offset or overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (posn_offset > sdev->stream_box.size ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) posn_offset % sizeof(struct sof_ipc_stream_posn) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) hda_stream->stream.posn_offset = sdev->stream_box.offset + posn_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_dbg(sdev->dev, "pcm: stream dir %d, posn mailbox offset is %zu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) substream->stream, hda_stream->stream.posn_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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