^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright(c) 2018 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) // Rander Wang <rander.wang@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) // Keyon Jie <yang.jie@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Hardware interface for generic Intel audio DSP HDA IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/hdaudio_ext.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/hda_register.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "../sof-audio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "../ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "hda.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "hda-ipc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static bool hda_enable_trace_D0I3_S0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) module_param_named(enable_trace_D0I3_S0, hda_enable_trace_D0I3_S0, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_PARM_DESC(enable_trace_D0I3_S0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) "SOF HDA enable trace when the DSP is in D0I3 in S0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * DSP Core control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 adspcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* set reset bits for cores */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) HDA_DSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) reset, reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* poll with timeout to check if operation successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) HDA_DSP_REG_ADSPCS, adspcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ((adspcs & reset) == reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) HDA_DSP_REG_POLL_INTERVAL_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) HDA_DSP_RESET_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* has core entered reset ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) HDA_DSP_REG_ADSPCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) HDA_DSP_ADSPCS_CRST_MASK(core_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "error: reset enter failed: core_mask %x adspcs 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) core_mask, adspcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int crst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 adspcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* clear reset bits for cores */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) HDA_DSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) HDA_DSP_ADSPCS_CRST_MASK(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* poll with timeout to check if operation successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) HDA_DSP_REG_ADSPCS, adspcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) !(adspcs & crst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) HDA_DSP_REG_POLL_INTERVAL_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) HDA_DSP_RESET_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* has core left reset ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) HDA_DSP_REG_ADSPCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "error: reset leave failed: core_mask %x adspcs 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) core_mask, adspcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* stall core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) HDA_DSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* set reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return hda_dsp_core_reset_enter(sdev, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* leave reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ret = hda_dsp_core_reset_leave(sdev, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* run core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) HDA_DSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* is core now running ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (!hda_dsp_core_is_enabled(sdev, core_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) hda_dsp_core_stall_reset(sdev, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * Power Management.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned int cpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 adspcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* update bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) HDA_DSP_ADSPCS_SPA_MASK(core_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) HDA_DSP_ADSPCS_SPA_MASK(core_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* poll with timeout to check if operation successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) HDA_DSP_REG_ADSPCS, adspcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) (adspcs & cpa) == cpa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) HDA_DSP_REG_POLL_INTERVAL_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) HDA_DSP_RESET_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* did core power up ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) HDA_DSP_REG_ADSPCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) HDA_DSP_ADSPCS_CPA_MASK(core_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "error: power up core failed core_mask %xadspcs 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) core_mask, adspcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 adspcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* update bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) HDA_DSP_REG_ADSPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) HDA_DSP_REG_ADSPCS, adspcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) !(adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) HDA_DSP_REG_POLL_INTERVAL_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) bool is_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MASK_IS_EQUAL(v, m, field) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 _m = field(m); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ((v) & _m) == _m; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) is_enable = MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_CPA_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_SPA_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) !(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) !(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #undef MASK_IS_EQUAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) is_enable, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return is_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) const struct sof_intel_dsp_desc *chip = hda->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* restrict core_mask to host managed cores mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) core_mask &= chip->host_managed_cores_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* return if core_mask is not valid or cores are already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!core_mask || hda_dsp_core_is_enabled(sdev, core_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ret = hda_dsp_core_power_up(sdev, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return hda_dsp_core_run(sdev, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) const struct sof_intel_dsp_desc *chip = hda->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* restrict core_mask to host managed cores mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) core_mask &= chip->host_managed_cores_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* return if core_mask is not valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (!core_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* place core in reset prior to power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ret = hda_dsp_core_stall_reset(sdev, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* power down core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ret = hda_dsp_core_power_down(sdev, core_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) core_mask, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* make sure we are in OFF state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (hda_dsp_core_is_enabled(sdev, core_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) core_mask, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) const struct sof_intel_dsp_desc *chip = hda->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* enable IPC DONE and BUSY interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* enable IPC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) const struct sof_intel_dsp_desc *chip = hda->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* disable IPC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) HDA_DSP_ADSPIC_IPC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* disable IPC BUSY and DONE interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct hdac_bus *bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int retry = HDA_DSP_REG_POLL_RETRY_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) while (snd_hdac_chip_readb(bus, VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (!retry--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) usleep_range(10, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct sof_ipc_pm_gate pm_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct sof_ipc_reply reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) memset(&pm_gate, 0, sizeof(pm_gate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* configure pm_gate ipc message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) pm_gate.hdr.size = sizeof(pm_gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pm_gate.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* send pm_gate ipc to dsp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return sof_ipc_tx_message_no_pm(sdev->ipc, pm_gate.hdr.cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) &pm_gate, sizeof(pm_gate), &reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) sizeof(reply));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct hdac_bus *bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Write to D0I3C after Command-In-Progress bit is cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ret = hda_dsp_wait_d0i3c_done(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev_err(bus->dev, "CIP timeout before D0I3C update!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Update D0I3C register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Wait for cmd in progress to be cleared before exiting the function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = hda_dsp_wait_d0i3c_done(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_err(bus->dev, "CIP timeout after D0I3C update!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_vdbg(bus->dev, "D0I3C updated, register = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) snd_hdac_chip_readb(bus, VS_D0I3C));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) const struct sof_dsp_power_state *target_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u32 flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u8 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * Sanity check for illegal state transitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * The only allowed transitions are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * 1. D3 -> D0I0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * 2. D0I0 -> D0I3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * 3. D0I3 -> D0I0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) switch (sdev->dsp_power_state.state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case SOF_DSP_PM_D0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Follow the sequence below for D0 substate transitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case SOF_DSP_PM_D3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Follow regular flow for D3 -> D0 transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_err(sdev->dev, "error: transition from %d to %d not allowed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) sdev->dsp_power_state.state, target_state->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Set flags and register value for D0 target substate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (target_state->substate == SOF_HDA_DSP_PM_D0I3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) value = SOF_HDA_VS_D0I3C_I3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * Trace DMA need to be disabled when the DSP enters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * D0I3 for S0Ix suspend, but it can be kept enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * when the DSP enters D0I3 while the system is in S0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * for debug purpose.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!sdev->dtrace_is_supported ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) !hda_enable_trace_D0I3_S0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) sdev->system_suspend_target != SOF_SUSPEND_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) flags = HDA_PM_NO_DMA_TRACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* prevent power gating in D0I0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) flags = HDA_PM_PPG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* update D0I3C register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ret = hda_dsp_update_d0i3c_register(sdev, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * Notify the DSP of the state change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * If this IPC fails, revert the D0I3C register update in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * to prevent partial state change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = hda_dsp_send_pm_gate_ipc(sdev, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "error: PM_GATE ipc error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) goto revert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) revert:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* fallback to the previous register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) value = value ? 0 : SOF_HDA_VS_D0I3C_I3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * This can fail but return the IPC error to signal that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * the state change failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) hda_dsp_update_d0i3c_register(sdev, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* helper to log DSP state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static void hda_dsp_state_log(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) switch (sdev->dsp_power_state.state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) case SOF_DSP_PM_D0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) switch (sdev->dsp_power_state.substate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case SOF_HDA_DSP_PM_D0I0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev_dbg(sdev->dev, "Current DSP power state: D0I0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) case SOF_HDA_DSP_PM_D0I3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_dbg(sdev->dev, "Current DSP power state: D0I3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_dbg(sdev->dev, "Unknown DSP D0 substate: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) sdev->dsp_power_state.substate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) case SOF_DSP_PM_D1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_dbg(sdev->dev, "Current DSP power state: D1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) case SOF_DSP_PM_D2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dev_dbg(sdev->dev, "Current DSP power state: D2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case SOF_DSP_PM_D3_HOT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_dbg(sdev->dev, "Current DSP power state: D3_HOT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) case SOF_DSP_PM_D3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dev_dbg(sdev->dev, "Current DSP power state: D3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case SOF_DSP_PM_D3_COLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_dbg(sdev->dev, "Current DSP power state: D3_COLD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dev_dbg(sdev->dev, "Unknown DSP power state: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) sdev->dsp_power_state.state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * All DSP power state transitions are initiated by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * If the requested state change fails, the error is simply returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * Further state transitions are attempted only when the set_power_save() op
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * is called again either because of a new IPC sent to the DSP or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * during system suspend/resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) const struct sof_dsp_power_state *target_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * When the DSP is already in D0I3 and the target state is D0I3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * it could be the case that the DSP is in D0I3 during S0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * and the system is suspending to S0Ix. Therefore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * hda_dsp_set_D0_state() must be called to disable trace DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * by sending the PM_GATE IPC to the FW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (target_state->substate == SOF_HDA_DSP_PM_D0I3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) sdev->system_suspend_target == SOF_SUSPEND_S0IX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) goto set_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * For all other cases, return without doing anything if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * the DSP is already in the target state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (target_state->state == sdev->dsp_power_state.state &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) target_state->substate == sdev->dsp_power_state.substate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) set_state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) switch (target_state->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) case SOF_DSP_PM_D0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = hda_dsp_set_D0_state(sdev, target_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case SOF_DSP_PM_D3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* The only allowed transition is: D0I0 -> D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) "error: transition from %d to %d not allowed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) sdev->dsp_power_state.state, target_state->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dev_err(sdev->dev, "error: target state unsupported %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) target_state->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) "failed to set requested target DSP state %d substate %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) target_state->state, target_state->substate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) sdev->dsp_power_state = *target_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) hda_dsp_state_log(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * Audio DSP states may transform as below:-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * Opportunistic D0I3 in S0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * Runtime +---------------------+ Delayed D0i3 work timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * suspend | +--------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * +------------+ D0I0(active) | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * | | <---------------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * | +--------> | New IPC | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * | |Runtime +--^--+---------^--+--+ (via mailbox) | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * | |resume | | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * | | | | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * | | System| | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * | | resume| | S3/S0IX | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * | | | | suspend | | S0IX | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * | | | | | |suspend | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * | | | | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * | | | | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * +-v---+-----------+--v-------+ | | +------+----v----+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * | | | +-----------> |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * | D3 (suspended) | | | D0I3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * | | +--------------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * | | System resume | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * +----------------------------+ +----------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * ignored the suspend trigger. Otherwise the DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * is in D3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) const struct sof_intel_dsp_desc *chip = hda->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct hdac_bus *bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) hda_sdw_int_enable(sdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* disable IPC interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) hda_dsp_ipc_int_disable(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (runtime_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) hda_codec_jack_wake_enable(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* power down all hda link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) snd_hdac_ext_bus_link_power_down_all(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* power down DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) "error: failed to power down core during suspend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* disable ppcap interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) hda_dsp_ctrl_ppcap_enable(sdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) hda_dsp_ctrl_ppcap_int_enable(sdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* disable hda bus irq and streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) hda_dsp_ctrl_stop_chip(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* disable LP retention mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) snd_sof_pci_update_bits(sdev, PCI_PGCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* reset controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ret = hda_dsp_ctrl_link_reset(sdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) "error: failed to reset controller during suspend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* display codec can powered off after link reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) hda_codec_i915_display_power(sdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct hdac_bus *bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct hdac_ext_link *hlink = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* display codec must be powered before link reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) hda_codec_i915_display_power(sdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * clear TCSEL to clear playback on some HD Audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * codecs. PCI TCSEL is defined in the Intel manuals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* reset and start hda controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ret = hda_dsp_ctrl_init_chip(sdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) "error: failed to start controller after resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* check jack status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (runtime_resume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (sdev->system_suspend_target == SOF_SUSPEND_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) hda_codec_jack_check(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* turn off the links that were off before suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) list_for_each_entry(hlink, &bus->hlink_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (!hlink->ref_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) snd_hdac_ext_bus_link_power_down(hlink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* check dma status and clean up CORB/RIRB buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (!bus->cmd_dma_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) snd_hdac_bus_stop_cmd_io(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* enable ppcap interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) hda_dsp_ctrl_ppcap_enable(sdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) hda_dsp_ctrl_ppcap_int_enable(sdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int hda_dsp_resume(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct pci_dev *pci = to_pci_dev(sdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) const struct sof_dsp_power_state target_state = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .state = SOF_DSP_PM_D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .substate = SOF_HDA_DSP_PM_D0I0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct hdac_bus *bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct hdac_ext_link *hlink = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* resume from D0I3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) hda_codec_i915_display_power(sdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* power up links that were active before suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) list_for_each_entry(hlink, &bus->hlink_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (hlink->ref_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ret = snd_hdac_ext_bus_link_power_up(hlink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dev_dbg(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "error %x in %s: failed to power up links",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ret, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* set up CORB/RIRB buffers if was on before suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (bus->cmd_dma_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) snd_hdac_bus_init_cmd_io(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* Set DSP power state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ret = snd_sof_dsp_set_power_state(sdev, &target_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) target_state.state, target_state.substate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* restore L1SEN bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (hda->l1_support_changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) HDA_VS_INTEL_EM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) HDA_VS_INTEL_EM2_L1SEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* restore and disable the system wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) pci_restore_state(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) disable_irq_wake(pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* init hda controller. DSP cores will be powered up during fw boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ret = hda_resume(sdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return snd_sof_dsp_set_power_state(sdev, &target_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) const struct sof_dsp_power_state target_state = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .state = SOF_DSP_PM_D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* init hda controller. DSP cores will be powered up during fw boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ret = hda_resume(sdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return snd_sof_dsp_set_power_state(sdev, &target_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) int hda_dsp_runtime_idle(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct hdac_bus *hbus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (hbus->codec_powered) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) (unsigned int)hbus->codec_powered);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) const struct sof_dsp_power_state target_state = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .state = SOF_DSP_PM_D3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* cancel any attempt for DSP D0I3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) cancel_delayed_work_sync(&hda->d0i3_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* stop hda controller and power dsp off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ret = hda_suspend(sdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return snd_sof_dsp_set_power_state(sdev, &target_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct hdac_bus *bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct pci_dev *pci = to_pci_dev(sdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) const struct sof_dsp_power_state target_dsp_state = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .state = target_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .substate = target_state == SOF_DSP_PM_D0 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) SOF_HDA_DSP_PM_D0I3 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* cancel any attempt for DSP D0I3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) cancel_delayed_work_sync(&hda->d0i3_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (target_state == SOF_DSP_PM_D0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* we can't keep a wakeref to display driver at suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) hda_codec_i915_display_power(sdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* Set DSP power state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ret = snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) target_dsp_state.state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) target_dsp_state.substate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* enable L1SEN to make sure the system can enter S0Ix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) hda->l1_support_changed =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) HDA_VS_INTEL_EM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) HDA_VS_INTEL_EM2_L1SEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) HDA_VS_INTEL_EM2_L1SEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* stop the CORB/RIRB DMA if it is On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (bus->cmd_dma_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) snd_hdac_bus_stop_cmd_io(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* no link can be powered in s0ix state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ret = snd_hdac_ext_bus_link_power_down_all(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dev_dbg(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) "error %d in %s: failed to power down links",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* enable the system waking up via IPC IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) enable_irq_wake(pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) pci_save_state(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* stop hda controller and power dsp off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ret = hda_suspend(sdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dev_err(bus->dev, "error: suspending dsp\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct hdac_bus *bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct snd_soc_pcm_runtime *rtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct hdac_ext_stream *stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct hdac_ext_link *link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct hdac_stream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) int stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* set internal flag for BE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) list_for_each_entry(s, &bus->stream_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) stream = stream_to_hdac_ext_stream(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * clear stream. This should already be taken care for running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * streams when the SUSPEND trigger is called. But paused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * streams do not get suspended, so this needs to be done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * explicitly during suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (stream->link_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) rtd = asoc_substream_to_rtd(stream->link_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) name = asoc_rtd_to_codec(rtd, 0)->component->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) link = snd_hdac_ext_bus_get_link(bus, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (!link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) stream->link_prepared = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (hdac_stream(stream)->direction ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) stream_tag = hdac_stream(stream)->stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) snd_hdac_ext_link_clear_stream_id(link, stream_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) void hda_dsp_d0i3_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct sof_intel_hda_dev *hdev = container_of(work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct sof_intel_hda_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) d0i3_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct hdac_bus *bus = &hdev->hbus.core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct sof_dsp_power_state target_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) target_state.state = SOF_DSP_PM_D0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* DSP can enter D0I3 iff only D0I3-compatible streams are active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (snd_sof_dsp_only_d0i3_compatible_stream_active(sdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) target_state.substate = SOF_HDA_DSP_PM_D0I3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) target_state.substate = SOF_HDA_DSP_PM_D0I0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* remain in D0I0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (target_state.substate == SOF_HDA_DSP_PM_D0I0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* This can fail but error cannot be propagated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ret = snd_sof_dsp_set_power_state(sdev, &target_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dev_err_ratelimited(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) "error: failed to set DSP state %d substate %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) target_state.state, target_state.substate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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