Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // This file is provided under a dual BSD/GPLv2 license.  When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // Copyright(c) 2018 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) //	    Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) //	    Rander Wang <rander.wang@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) //          Keyon Jie <yang.jie@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * Hardware interface for generic Intel audio DSP HDA IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <sound/hdaudio_ext.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <sound/hda_register.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <sound/hda_component.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "../ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "hda.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static int hda_codec_mask = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) module_param_named(codec_mask, hda_codec_mask, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) MODULE_PARM_DESC(codec_mask, "SOF HDA codec mask for probing");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * HDA Operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u32 gctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	/* 0 to enter reset and 1 to exit reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	val = reset ? 0 : SOF_HDA_GCTL_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	/* enter/exit HDA controller reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 				SOF_HDA_GCTL_RESET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	/* wait to enter/exit reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	timeout = jiffies + msecs_to_jiffies(HDA_DSP_CTRL_RESET_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		if ((gctl & SOF_HDA_GCTL_RESET) == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	/* enter/exit reset failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	dev_err(sdev->dev, "error: failed to %s HDA controller gctl 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		reset ? "reset" : "ready", gctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct hdac_bus *bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u32 cap, offset, feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 * On some devices, one reset cycle is necessary before reading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 * capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	ret = hda_dsp_ctrl_link_reset(sdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	ret = hda_dsp_ctrl_link_reset(sdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	offset = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_LLCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		dev_dbg(sdev->dev, "checking for capabilities at offset 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			offset & SOF_HDA_CAP_NEXT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		cap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		if (cap == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			dev_dbg(bus->dev, "Invalid capability reg read\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		feature = (cap & SOF_HDA_CAP_ID_MASK) >> SOF_HDA_CAP_ID_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		switch (feature) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		case SOF_HDA_PP_CAP_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			dev_dbg(sdev->dev, "found DSP capability at 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			bus->ppcap = bus->remap_addr + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			sdev->bar[HDA_DSP_PP_BAR] = bus->ppcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		case SOF_HDA_SPIB_CAP_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			dev_dbg(sdev->dev, "found SPIB capability at 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 				offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			bus->spbcap = bus->remap_addr + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			sdev->bar[HDA_DSP_SPIB_BAR] = bus->spbcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		case SOF_HDA_DRSM_CAP_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			dev_dbg(sdev->dev, "found DRSM capability at 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 				offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			bus->drsmcap = bus->remap_addr + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			sdev->bar[HDA_DSP_DRSM_BAR] = bus->drsmcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		case SOF_HDA_GTS_CAP_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			dev_dbg(sdev->dev, "found GTS capability at 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 				offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			bus->gtscap = bus->remap_addr + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		case SOF_HDA_ML_CAP_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			dev_dbg(sdev->dev, "found ML capability at 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 				offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			bus->mlcap = bus->remap_addr + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			dev_dbg(sdev->dev, "found capability %d at 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				feature, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		offset = cap & SOF_HDA_CAP_NEXT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	} while (count++ <= SOF_HDA_MAX_CAPS && offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	u32 val = enable ? SOF_HDA_PPCTL_GPROCEN : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 				SOF_HDA_PPCTL_GPROCEN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	u32 val	= enable ? SOF_HDA_PPCTL_PIE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 				SOF_HDA_PPCTL_PIE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u32 val = enable ? PCI_CGCTL_MISCBDCGE_MASK : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_MISCBDCGE_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  * enable/disable audio dsp clock gating and power gating bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  * This allows the HW to opportunistically power and clock gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  * the audio dsp when it is idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	/* enable/disable audio dsp clock gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	val = enable ? PCI_CGCTL_ADSPDCGE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_ADSPDCGE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	/* enable/disable DMI Link L1 support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	val = enable ? HDA_VS_INTEL_EM2_L1SEN : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 				HDA_VS_INTEL_EM2_L1SEN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/* enable/disable audio dsp power gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	val = enable ? 0 : PCI_PGCTL_ADSPPGD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	snd_sof_pci_update_bits(sdev, PCI_PGCTL, PCI_PGCTL_ADSPPGD, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct hdac_bus *bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct hdac_ext_link *hlink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct hdac_stream *stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	int sd_offset, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (bus->chip_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	snd_hdac_set_codec_wakeup(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	hda_dsp_ctrl_misc_clock_gating(sdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (full_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		/* reset HDA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		ret = hda_dsp_ctrl_link_reset(sdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			dev_err(sdev->dev, "error: failed to reset HDA controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		/* exit HDA controller reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		ret = hda_dsp_ctrl_link_reset(sdev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			dev_err(sdev->dev, "error: failed to exit HDA controller reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		usleep_range(1000, 1200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* check to see if controller is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (!snd_hdac_chip_readb(bus, GCTL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		dev_dbg(bus->dev, "controller not ready!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/* Accept unsolicited responses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	/* detect codecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (!bus->codec_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (hda_codec_mask != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		bus->codec_mask &= hda_codec_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		dev_dbg(bus->dev, "filtered codec_mask = 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			bus->codec_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	/* clear stream status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	list_for_each_entry(stream, &bus->stream_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		sd_offset = SOF_STREAM_SD_OFFSET(stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 				  sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 				  SOF_HDA_CL_DMA_SD_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	/* clear WAKESTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			  SOF_HDA_WAKESTS_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	/* clear rirb status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	/* clear interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			  SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_ALL_STREAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	/* initialize the codec command I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	snd_hdac_bus_init_cmd_io(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	/* enable CIE and GIE interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 				SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 				SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	/* program the position buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (bus->use_posbuf && bus->posbuf.addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 				  (u32)bus->posbuf.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 				  upper_32_bits(bus->posbuf.addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	/* Reset stream-to-link mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	list_for_each_entry(hlink, &bus->hlink_list, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	bus->chip_init = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	hda_dsp_ctrl_misc_clock_gating(sdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	snd_hdac_set_codec_wakeup(bus, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	struct hdac_bus *bus = sof_to_bus(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	struct hdac_stream *stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	int sd_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (!bus->chip_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	/* disable interrupts in stream descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	list_for_each_entry(stream, &bus->stream_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		sd_offset = SOF_STREAM_SD_OFFSET(stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 					sd_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 					SOF_HDA_ADSP_REG_CL_SD_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 					SOF_HDA_CL_DMA_SD_INT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 					0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	/* disable SIE for all streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 				SOF_HDA_INT_ALL_STREAM,	0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	/* disable controller CIE and GIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 				SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 				0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	/* clear stream status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	list_for_each_entry(stream, &bus->stream_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		sd_offset = SOF_STREAM_SD_OFFSET(stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 				  sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 				  SOF_HDA_CL_DMA_SD_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	/* clear WAKESTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			  SOF_HDA_WAKESTS_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	/* clear rirb status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	/* clear interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 			  SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_ALL_STREAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	/* disable CORB/RIRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	snd_hdac_bus_stop_cmd_io(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	/* disable position buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	if (bus->posbuf.addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 				  SOF_HDA_ADSP_DPLBASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 				  SOF_HDA_ADSP_DPUBASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	bus->chip_init = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }