^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright(c) 2018 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) // Rander Wang <rander.wang@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) // Keyon Jie <yang.jie@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Hardware interface for audio DSP on Cannonlake.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "../ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "hda.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "hda-ipc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "../sof-audio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static const struct snd_sof_debugfs_map cnl_dsp_debugfs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static void cnl_ipc_host_done(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct snd_sof_dev *sdev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 hipci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 hipcida;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 hipctdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 hipctdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 msg_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) bool ipc_irq = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* reply message from DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (hipcida & CNL_DSP_REG_HIPCIDA_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) msg_ext = hipci & CNL_DSP_REG_HIPCIDR_MSG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) msg = hipcida & CNL_DSP_REG_HIPCIDA_MSG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) dev_vdbg(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "ipc: firmware response, msg:0x%x, msg_ext:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) msg, msg_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* mask Done interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) CNL_DSP_REG_HIPCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) CNL_DSP_REG_HIPCCTL_DONE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) spin_lock_irq(&sdev->ipc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* handle immediate reply from DSP core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) hda_dsp_ipc_get_reply(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) snd_sof_ipc_reply(sdev, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) cnl_ipc_dsp_done(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) spin_unlock_irq(&sdev->ipc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ipc_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* new message from DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) msg = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) msg_ext = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dev_vdbg(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "ipc: firmware initiated, msg:0x%x, msg_ext:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) msg, msg_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* handle messages from DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if ((hipctdr & SOF_IPC_PANIC_MAGIC_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SOF_IPC_PANIC_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) snd_sof_ipc_msgs_rx(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) cnl_ipc_host_done(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ipc_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (!ipc_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * This interrupt is not shared so no need to return IRQ_NONE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dev_dbg_ratelimited(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "nothing to do in IPC IRQ thread\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void cnl_ipc_host_done(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * clear busy interrupt to tell dsp controller this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * interrupt has been accepted, not trigger it again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) CNL_DSP_REG_HIPCTDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) CNL_DSP_REG_HIPCTDR_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) CNL_DSP_REG_HIPCTDR_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * set done bit to ack dsp the msg has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * processed and send reply msg to dsp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) CNL_DSP_REG_HIPCTDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) CNL_DSP_REG_HIPCTDA_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) CNL_DSP_REG_HIPCTDA_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * set DONE bit - tell DSP we have received the reply msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * from DSP, and processed it, don't send more reply to host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) CNL_DSP_REG_HIPCIDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) CNL_DSP_REG_HIPCIDA_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) CNL_DSP_REG_HIPCIDA_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* unmask Done interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) CNL_DSP_REG_HIPCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) CNL_DSP_REG_HIPCCTL_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CNL_DSP_REG_HIPCCTL_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static bool cnl_compact_ipc_compress(struct snd_sof_ipc_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 *dr, u32 *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct sof_ipc_pm_gate *pm_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (msg->header == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pm_gate = msg->msg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* send the compact message via the primary register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) *dr = HDA_IPC_MSG_COMPACT | HDA_IPC_PM_GATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* send payload via the extended data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) *dd = pm_gate->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct sof_ipc_cmd_hdr *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 dr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 dd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Currently the only compact IPC supported is the PM_GATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * IPC which is used for transitioning the DSP between the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * D0I0 and D0I3 states. And these are sent only during the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * set_power_state() op. Therefore, there will never be a case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * that a compact IPC results in the DSP exiting D0I3 without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * the host and FW being in sync.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (cnl_compact_ipc_compress(msg, &dr, &dd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* send the message via IPC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) CNL_DSP_REG_HIPCIDR_BUSY | dr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* send the message via mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) msg->msg_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) CNL_DSP_REG_HIPCIDR_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) hdr = msg->msg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Use mod_delayed_work() to schedule the delayed work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * to avoid scheduling multiple workqueue items when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * IPCs are sent at a high-rate. mod_delayed_work()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * modifies the timer if the work is pending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Also, a new delayed work should not be queued after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * CTX_SAVE IPC, which is sent before the DSP enters D3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (hdr->cmd != (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) mod_delayed_work(system_wq, &hdev->d0i3_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) msecs_to_jiffies(SOF_HDA_D0I3_WORK_DELAY_MS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) void cnl_ipc_dump(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 hipcctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 hipcida;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 hipctdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) hda_ipc_irq_dump(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* read IPC status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* dump the IPC regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* TODO: parse the raw msg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) hipcida, hipctdr, hipcctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* cannonlake ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) const struct snd_sof_dsp_ops sof_cnl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* probe and remove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .probe = hda_dsp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .remove = hda_dsp_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Register IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .write = sof_io_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .read = sof_io_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .write64 = sof_io_write64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .read64 = sof_io_read64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Block IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .block_read = sof_block_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .block_write = sof_block_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .irq_thread = cnl_ipc_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* ipc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .send_msg = cnl_ipc_send_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .fw_ready = sof_fw_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .get_window_offset = hda_dsp_ipc_get_window_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .ipc_msg_data = hda_ipc_msg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .ipc_pcm_params = hda_ipc_pcm_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* machine driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .machine_select = hda_machine_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .machine_register = sof_machine_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .machine_unregister = sof_machine_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .set_mach_params = hda_set_mach_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .debug_map = cnl_dsp_debugfs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .debug_map_count = ARRAY_SIZE(cnl_dsp_debugfs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .dbg_dump = hda_dsp_dump,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .ipc_dump = cnl_ipc_dump,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* stream callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .pcm_open = hda_dsp_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .pcm_close = hda_dsp_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .pcm_hw_params = hda_dsp_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .pcm_hw_free = hda_dsp_stream_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .pcm_trigger = hda_dsp_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .pcm_pointer = hda_dsp_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* probe callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .probe_assign = hda_probe_compr_assign,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .probe_free = hda_probe_compr_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .probe_set_params = hda_probe_compr_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .probe_trigger = hda_probe_compr_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .probe_pointer = hda_probe_compr_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* firmware loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .load_firmware = snd_sof_load_firmware_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* pre/post fw run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .pre_fw_run = hda_dsp_pre_fw_run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .post_fw_run = hda_dsp_post_fw_run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* dsp core power up/down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .core_power_up = hda_dsp_enable_core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .core_power_down = hda_dsp_core_reset_power_down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* firmware run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .run = hda_dsp_cl_boot_firmware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* trace callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .trace_init = hda_dsp_trace_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .trace_release = hda_dsp_trace_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .trace_trigger = hda_dsp_trace_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* DAI drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .drv = skl_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .num_drv = SOF_SKL_NUM_DAIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .suspend = hda_dsp_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .resume = hda_dsp_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .runtime_suspend = hda_dsp_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .runtime_resume = hda_dsp_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .runtime_idle = hda_dsp_runtime_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .set_power_state = hda_dsp_set_power_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* ALSA HW info flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .hw_info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .arch_ops = &sof_xtensa_arch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) EXPORT_SYMBOL_NS(sof_cnl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) const struct sof_intel_dsp_desc cnl_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Cannonlake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .cores_num = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .init_core_mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .host_managed_cores_mask = GENMASK(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .ipc_req = CNL_DSP_REG_HIPCIDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .ipc_ack = CNL_DSP_REG_HIPCIDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .ipc_ctl = CNL_DSP_REG_HIPCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .rom_init_timeout = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .ssp_count = CNL_SSP_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .ssp_base_offset = CNL_SSP_BASE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) const struct sof_intel_dsp_desc icl_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Icelake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .cores_num = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .init_core_mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .host_managed_cores_mask = GENMASK(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .ipc_req = CNL_DSP_REG_HIPCIDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .ipc_ack = CNL_DSP_REG_HIPCIDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .ipc_ctl = CNL_DSP_REG_HIPCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .rom_init_timeout = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .ssp_count = ICL_SSP_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .ssp_base_offset = CNL_SSP_BASE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) const struct sof_intel_dsp_desc ehl_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Elkhartlake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .cores_num = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .init_core_mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .host_managed_cores_mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .ipc_req = CNL_DSP_REG_HIPCIDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .ipc_ack = CNL_DSP_REG_HIPCIDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .ipc_ctl = CNL_DSP_REG_HIPCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .rom_init_timeout = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .ssp_count = ICL_SSP_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .ssp_base_offset = CNL_SSP_BASE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) const struct sof_intel_dsp_desc jsl_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Jasperlake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .cores_num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .init_core_mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .host_managed_cores_mask = GENMASK(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .ipc_req = CNL_DSP_REG_HIPCIDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .ipc_ack = CNL_DSP_REG_HIPCIDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .ipc_ctl = CNL_DSP_REG_HIPCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .rom_init_timeout = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .ssp_count = ICL_SSP_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .ssp_base_offset = CNL_SSP_BASE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags