^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright(c) 2018 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/sof.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/sof/xtensa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "../ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "shim.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "../sof-audio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "../../intel/common/soc-intel-quirks.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* DSP memories */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IRAM_OFFSET 0x0C0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IRAM_SIZE (80 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRAM_OFFSET 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRAM_SIZE (160 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SHIM_OFFSET 0x140000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SHIM_SIZE_BYT 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SHIM_SIZE_CHT 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MBOX_OFFSET 0x144000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MBOX_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EXCEPT_OFFSET 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EXCEPT_MAX_HDR_SIZE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* DSP peripherals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DMAC0_OFFSET 0x098000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DMAC1_OFFSET 0x09c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DMAC2_OFFSET 0x094000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DMAC_SIZE 0x420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SSP0_OFFSET 0x0a0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SSP1_OFFSET 0x0a1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SSP2_OFFSET 0x0a2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SSP3_OFFSET 0x0a4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SSP4_OFFSET 0x0a5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SSP5_OFFSET 0x0a6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SSP_SIZE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BYT_STACK_DUMP_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BYT_PCI_BAR_SIZE 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BYT_PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MBOX_DUMP_SIZE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* BARs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BYT_DSP_BAR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BYT_PCI_BAR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define BYT_IMR_BAR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const struct snd_sof_debugfs_map byt_debugfs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SOF_DEBUGFS_ACCESS_D0_ONLY},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SOF_DEBUGFS_ACCESS_D0_ONLY},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void byt_host_done(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void byt_dsp_done(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void byt_get_reply(struct snd_sof_dev *sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void byt_get_registers(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct sof_ipc_dsp_oops_xtensa *xoops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct sof_ipc_panic_info *panic_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 *stack, size_t stack_words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 offset = sdev->dsp_oops_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* first read regsisters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* note: variable AR register array is not read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* then get panic info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) xoops->arch_hdr.totalsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) offset += xoops->arch_hdr.totalsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* then get the stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) offset += sizeof(*panic_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void byt_dump(struct snd_sof_dev *sdev, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct sof_ipc_dsp_oops_xtensa xoops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct sof_ipc_panic_info panic_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 stack[BYT_STACK_DUMP_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u64 status, panic, imrd, imrx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* now try generic SOF status messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) status = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) panic = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) byt_get_registers(sdev, &xoops, &panic_info, stack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) BYT_STACK_DUMP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) BYT_STACK_DUMP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* provide some context for firmware debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) imrd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "error: ipc host -> DSP: pending %s complete %s raw 0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) (panic & SHIM_IPCX_BUSY) ? "yes" : "no",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) (panic & SHIM_IPCX_DONE) ? "yes" : "no", panic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "error: mask host: pending %s complete %s raw 0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) (imrx & SHIM_IMRX_BUSY) ? "yes" : "no",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) (imrx & SHIM_IMRX_DONE) ? "yes" : "no", imrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "error: ipc DSP -> host: pending %s complete %s raw 0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) (status & SHIM_IPCD_BUSY) ? "yes" : "no",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) (status & SHIM_IPCD_DONE) ? "yes" : "no", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "error: mask DSP: pending %s complete %s raw 0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) (imrd & SHIM_IMRD_BUSY) ? "yes" : "no",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) (imrd & SHIM_IMRD_DONE) ? "yes" : "no", imrd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * IPC Doorbell IRQ handler and thread.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static irqreturn_t byt_irq_handler(int irq, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct snd_sof_dev *sdev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u64 ipcx, ipcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (ipcx & SHIM_BYT_IPCX_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* reply message from DSP, Mask Done interrupt first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) SHIM_IMRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) SHIM_IMRX_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) SHIM_IMRX_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ret = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (ipcd & SHIM_BYT_IPCD_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* new message from DSP, Mask Busy interrupt first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) SHIM_IMRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) SHIM_IMRX_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) SHIM_IMRX_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ret = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static irqreturn_t byt_irq_thread(int irq, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct snd_sof_dev *sdev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u64 ipcx, ipcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* reply message from DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (ipcx & SHIM_BYT_IPCX_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) spin_lock_irq(&sdev->ipc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * handle immediate reply from DSP core. If the msg is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * found, set done bit in cmd_done which is called at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * end of message processing function, else set it here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * because the done bit can't be set in cmd_done function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * which is triggered by msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) byt_get_reply(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) snd_sof_ipc_reply(sdev, ipcx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) byt_dsp_done(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) spin_unlock_irq(&sdev->ipc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* new message from DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ipcd & SHIM_BYT_IPCD_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Handle messages from DSP Core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) snd_sof_dsp_panic(sdev, BYT_PANIC_OFFSET(ipcd) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MBOX_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) snd_sof_ipc_msgs_rx(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) byt_host_done(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* unmask and prepare to receive Done interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) SHIM_IMRX_DONE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* send the message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) msg->msg_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void byt_get_reply(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct snd_sof_ipc_msg *msg = sdev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct sof_ipc_reply reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * Sometimes, there is unexpected reply ipc arriving. The reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * ipc belongs to none of the ipcs sent from driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * In this case, the driver must ignore the ipc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* get reply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (reply.error < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) memcpy(msg->reply_data, &reply, sizeof(reply));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ret = reply.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* reply correct size ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (reply.hdr.size != msg->reply_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) msg->reply_size, reply.hdr.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* read the message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (msg->reply_size > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) sof_mailbox_read(sdev, sdev->host_box.offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) msg->reply_data, msg->reply_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) msg->reply_error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int byt_get_mailbox_offset(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return MBOX_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int byt_get_window_offset(struct snd_sof_dev *sdev, u32 id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return MBOX_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void byt_host_done(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* clear BUSY bit and set DONE bit - accept new messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) SHIM_BYT_IPCD_BUSY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) SHIM_BYT_IPCD_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) SHIM_BYT_IPCD_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* unmask and prepare to receive next new message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) SHIM_IMRX_BUSY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void byt_dsp_done(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* clear DONE bit - tell DSP we have completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) SHIM_BYT_IPCX_DONE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * DSP control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int byt_run(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int tries = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* release stall and wait to unstall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) SHIM_BYT_CSR_STALL, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) while (tries--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (!(snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_CSR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) SHIM_BYT_CSR_PWAITMODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (tries < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev_err(sdev->dev, "error: unable to run DSP firmware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) byt_dump(sdev, SOF_DBG_REGS | SOF_DBG_MBOX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* return init core mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int byt_reset(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* put DSP into reset, set reset vector and stall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) SHIM_BYT_CSR_STALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) SHIM_BYT_CSR_STALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) usleep_range(10, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* take DSP out of reset and keep stalled for FW loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) SHIM_BYT_CSR_RST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const char *fixup_tplg_name(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) const char *sof_tplg_filename,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) const char *ssp_str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) const char *tplg_filename = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) char *filename;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) char *split_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (!filename)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* this assumes a .tplg extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) split_ext = strsep(&filename, ".");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (split_ext) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "%s-%s.tplg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) split_ext, ssp_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (!tplg_filename)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return tplg_filename;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static void byt_machine_select(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct snd_sof_pdata *sof_pdata = sdev->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) const struct sof_dev_desc *desc = sof_pdata->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct snd_soc_acpi_mach *mach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) const char *tplg_filename;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) mach = snd_soc_acpi_find_machine(desc->machines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (!mach) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pdev = to_platform_device(sdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (soc_intel_is_byt_cr(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dev_dbg(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) "BYT-CR detected, SSP0 used instead of SSP2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) tplg_filename = fixup_tplg_name(sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) mach->sof_tplg_filename,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) "ssp0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) tplg_filename = mach->sof_tplg_filename;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!tplg_filename) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev_dbg(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) "error: no topology filename\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) sof_pdata->tplg_filename = tplg_filename;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) sof_pdata->machine = mach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static void byt_set_mach_params(const struct snd_soc_acpi_mach *mach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct snd_soc_acpi_mach_params *mach_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) mach_params = (struct snd_soc_acpi_mach_params *)&mach->mach_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) mach_params->platform = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Baytrail DAIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static struct snd_soc_dai_driver byt_dai[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .name = "ssp0-port",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .name = "ssp1-port",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .name = "ssp2-port",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .name = "ssp3-port",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .name = "ssp4-port",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .name = "ssp5-port",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * Probe and remove.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #if IS_ENABLED(CONFIG_SND_SOC_SOF_MERRIFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static int tangier_pci_probe(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct snd_sof_pdata *pdata = sdev->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) const struct sof_dev_desc *desc = pdata->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct pci_dev *pci = to_pci_dev(sdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u32 base, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* DSP DMA can only access low 31 bits of host memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ret = dma_coerce_mask_and_coherent(&pci->dev, DMA_BIT_MASK(31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* LPE base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) base = pci_resource_start(pci, desc->resindex_lpe_base) - IRAM_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) size = BYT_PCI_BAR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (!sdev->bar[BYT_DSP_BAR]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* IMR base - optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (desc->resindex_imr_base == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) goto irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) base = pci_resource_start(pci, desc->resindex_imr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) size = pci_resource_len(pci, desc->resindex_imr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* some BIOSes don't map IMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (base == 0x55aa55aa || base == 0x0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) goto irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (!sdev->bar[BYT_IMR_BAR]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* register our IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) sdev->ipc_irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) byt_irq_handler, byt_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 0, "AudioDSP", sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dev_err(sdev->dev, "error: failed to register IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) sdev->ipc_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* enable BUSY and disable DONE Interrupt by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) SHIM_IMRX_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* set default mailbox offset for FW ready message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) sdev->dsp_box.offset = MBOX_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) const struct snd_sof_dsp_ops sof_tng_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* device init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .probe = tangier_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* DSP core boot / reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .run = byt_run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .reset = byt_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* Register IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .write = sof_io_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .read = sof_io_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .write64 = sof_io_write64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .read64 = sof_io_read64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Block IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .block_read = sof_block_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .block_write = sof_block_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .irq_handler = byt_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .irq_thread = byt_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* ipc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .send_msg = byt_send_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .fw_ready = sof_fw_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .get_mailbox_offset = byt_get_mailbox_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .get_window_offset = byt_get_window_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .ipc_msg_data = intel_ipc_msg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .ipc_pcm_params = intel_ipc_pcm_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* machine driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .machine_select = byt_machine_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .machine_register = sof_machine_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .machine_unregister = sof_machine_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .set_mach_params = byt_set_mach_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .debug_map = byt_debugfs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .debug_map_count = ARRAY_SIZE(byt_debugfs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .dbg_dump = byt_dump,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* stream callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .pcm_open = intel_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .pcm_close = intel_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* module loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .load_module = snd_sof_parse_module_memcpy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /*Firmware loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .load_firmware = snd_sof_load_firmware_memcpy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* DAI drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .drv = byt_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .num_drv = 3, /* we have only 3 SSPs on byt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* ALSA HW info flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .hw_info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) SNDRV_PCM_INFO_BATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .arch_ops = &sof_xtensa_arch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) EXPORT_SYMBOL_NS(sof_tng_ops, SND_SOC_SOF_MERRIFIELD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) const struct sof_intel_dsp_desc tng_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .cores_num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .host_managed_cores_mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #endif /* CONFIG_SND_SOC_SOF_MERRIFIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* Disable Interrupt from both sides */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* Put DSP into reset, set reset vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static int byt_suspend(struct snd_sof_dev *sdev, u32 target_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) byt_reset_dsp_disable_int(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static int byt_resume(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* enable BUSY and disable DONE Interrupt by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) SHIM_IMRX_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static int byt_remove(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) byt_reset_dsp_disable_int(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static const struct snd_sof_debugfs_map cht_debugfs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {"dmac0", BYT_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {"dmac1", BYT_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {"dmac2", BYT_DSP_BAR, DMAC2_OFFSET, DMAC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {"ssp0", BYT_DSP_BAR, SSP0_OFFSET, SSP_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {"ssp1", BYT_DSP_BAR, SSP1_OFFSET, SSP_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {"ssp2", BYT_DSP_BAR, SSP2_OFFSET, SSP_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {"ssp3", BYT_DSP_BAR, SSP3_OFFSET, SSP_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {"ssp4", BYT_DSP_BAR, SSP4_OFFSET, SSP_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {"ssp5", BYT_DSP_BAR, SSP5_OFFSET, SSP_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {"iram", BYT_DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) SOF_DEBUGFS_ACCESS_D0_ONLY},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {"dram", BYT_DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) SOF_DEBUGFS_ACCESS_D0_ONLY},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {"shim", BYT_DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) SOF_DEBUGFS_ACCESS_ALWAYS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static int byt_acpi_probe(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct snd_sof_pdata *pdata = sdev->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) const struct sof_dev_desc *desc = pdata->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct platform_device *pdev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) container_of(sdev->dev, struct platform_device, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct resource *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u32 base, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* DSP DMA can only access low 31 bits of host memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* LPE base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) mmio = platform_get_resource(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) desc->resindex_lpe_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) base = mmio->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) size = resource_size(mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) desc->resindex_lpe_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (!sdev->bar[BYT_DSP_BAR]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* TODO: add offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) sdev->mmio_bar = BYT_DSP_BAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) sdev->mailbox_bar = BYT_DSP_BAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* IMR base - optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (desc->resindex_imr_base == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) goto irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) mmio = platform_get_resource(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) desc->resindex_imr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) base = mmio->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) size = resource_size(mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) desc->resindex_imr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* some BIOSes don't map IMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (base == 0x55aa55aa || base == 0x0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) goto irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (!sdev->bar[BYT_IMR_BAR]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* register our IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (sdev->ipc_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return sdev->ipc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) byt_irq_handler, byt_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) IRQF_SHARED, "AudioDSP", sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev_err(sdev->dev, "error: failed to register IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) sdev->ipc_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* enable BUSY and disable DONE Interrupt by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) SHIM_IMRX_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* set default mailbox offset for FW ready message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) sdev->dsp_box.offset = MBOX_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* baytrail ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) const struct snd_sof_dsp_ops sof_byt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* device init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .probe = byt_acpi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .remove = byt_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* DSP core boot / reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .run = byt_run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .reset = byt_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* Register IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .write = sof_io_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .read = sof_io_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .write64 = sof_io_write64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .read64 = sof_io_read64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* Block IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .block_read = sof_block_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .block_write = sof_block_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .irq_handler = byt_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .irq_thread = byt_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* ipc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .send_msg = byt_send_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .fw_ready = sof_fw_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .get_mailbox_offset = byt_get_mailbox_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .get_window_offset = byt_get_window_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .ipc_msg_data = intel_ipc_msg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .ipc_pcm_params = intel_ipc_pcm_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* machine driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .machine_select = byt_machine_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .machine_register = sof_machine_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .machine_unregister = sof_machine_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .set_mach_params = byt_set_mach_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .debug_map = byt_debugfs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .debug_map_count = ARRAY_SIZE(byt_debugfs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .dbg_dump = byt_dump,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* stream callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .pcm_open = intel_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .pcm_close = intel_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* module loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .load_module = snd_sof_parse_module_memcpy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /*Firmware loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .load_firmware = snd_sof_load_firmware_memcpy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .suspend = byt_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .resume = byt_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* DAI drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .drv = byt_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .num_drv = 3, /* we have only 3 SSPs on byt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* ALSA HW info flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .hw_info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) SNDRV_PCM_INFO_BATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .arch_ops = &sof_xtensa_arch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) EXPORT_SYMBOL_NS(sof_byt_ops, SND_SOC_SOF_BAYTRAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) const struct sof_intel_dsp_desc byt_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .cores_num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .host_managed_cores_mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) EXPORT_SYMBOL_NS(byt_chip_info, SND_SOC_SOF_BAYTRAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /* cherrytrail and braswell ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) const struct snd_sof_dsp_ops sof_cht_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* device init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .probe = byt_acpi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .remove = byt_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* DSP core boot / reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .run = byt_run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .reset = byt_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* Register IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .write = sof_io_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .read = sof_io_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .write64 = sof_io_write64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .read64 = sof_io_read64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* Block IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .block_read = sof_block_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .block_write = sof_block_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .irq_handler = byt_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .irq_thread = byt_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* ipc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .send_msg = byt_send_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .fw_ready = sof_fw_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .get_mailbox_offset = byt_get_mailbox_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .get_window_offset = byt_get_window_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .ipc_msg_data = intel_ipc_msg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .ipc_pcm_params = intel_ipc_pcm_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* machine driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .machine_select = byt_machine_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .machine_register = sof_machine_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .machine_unregister = sof_machine_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .set_mach_params = byt_set_mach_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /* debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .debug_map = cht_debugfs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .debug_map_count = ARRAY_SIZE(cht_debugfs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .dbg_dump = byt_dump,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* stream callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .pcm_open = intel_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .pcm_close = intel_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* module loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .load_module = snd_sof_parse_module_memcpy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /*Firmware loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .load_firmware = snd_sof_load_firmware_memcpy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .suspend = byt_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .resume = byt_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* DAI drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .drv = byt_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* all 6 SSPs may be available for cherrytrail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .num_drv = ARRAY_SIZE(byt_dai),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* ALSA HW info flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .hw_info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) SNDRV_PCM_INFO_BATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .arch_ops = &sof_xtensa_arch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) EXPORT_SYMBOL_NS(sof_cht_ops, SND_SOC_SOF_BAYTRAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) const struct sof_intel_dsp_desc cht_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .cores_num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .host_managed_cores_mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) EXPORT_SYMBOL_NS(cht_chip_info, SND_SOC_SOF_BAYTRAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #endif /* CONFIG_SND_SOC_SOF_BAYTRAIL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) MODULE_LICENSE("Dual BSD/GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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