Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright 2020 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Author: Daniel Baluta <daniel.baluta@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // Hardware interface for audio DSP on i.MX8M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <sound/sof.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <sound/sof/xtensa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/firmware/imx/dsp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "../ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "imx-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MBOX_OFFSET	0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MBOX_SIZE	0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct imx8m_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct snd_sof_dev *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	/* DSP IPC handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct imx_dsp_ipc *dsp_ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct platform_device *ipc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static void imx8m_get_reply(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct snd_sof_ipc_msg *msg = sdev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct sof_ipc_reply reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	if (!msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		dev_warn(sdev->dev, "unexpected ipc interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	/* get reply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	if (reply.error < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		memcpy(msg->reply_data, &reply, sizeof(reply));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		ret = reply.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		/* reply has correct size? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		if (reply.hdr.size != msg->reply_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 				msg->reply_size, reply.hdr.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		/* read the message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		if (msg->reply_size > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 			sof_mailbox_read(sdev, sdev->host_box.offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 					 msg->reply_data, msg->reply_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	msg->reply_error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static int imx8m_get_mailbox_offset(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	return MBOX_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static int imx8m_get_window_offset(struct snd_sof_dev *sdev, u32 id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return MBOX_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static void imx8m_dsp_handle_reply(struct imx_dsp_ipc *ipc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct imx8m_priv *priv = imx_dsp_get_data(ipc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	imx8m_get_reply(priv->sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	snd_sof_ipc_reply(priv->sdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static void imx8m_dsp_handle_request(struct imx_dsp_ipc *ipc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct imx8m_priv *priv = imx_dsp_get_data(ipc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	u32 p; /* Panic code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	/* Read the message from the debug box. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, &p, sizeof(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/* Check to see if the message is a panic code (0x0dead***) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		snd_sof_dsp_panic(priv->sdev, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		snd_sof_ipc_msgs_rx(priv->sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct imx_dsp_ops imx8m_dsp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.handle_reply		= imx8m_dsp_handle_reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.handle_request		= imx8m_dsp_handle_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int imx8m_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct imx8m_priv *priv = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			  msg->msg_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	imx_dsp_ring_doorbell(priv->dsp_ipc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * DSP control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int imx8m_run(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* TODO: start DSP using Audio MIX bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int imx8m_probe(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct platform_device *pdev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		container_of(sdev->dev, struct platform_device, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct device_node *res_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct resource *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct imx8m_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	u32 base, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	sdev->pdata->hw_pdata = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	priv->dev = sdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	priv->sdev = sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	priv->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 						      PLATFORM_DEVID_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 						      pdev, sizeof(*pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (IS_ERR(priv->ipc_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		return PTR_ERR(priv->ipc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (!priv->dsp_ipc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		/* DSP IPC driver not probed yet, try later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		dev_err(sdev->dev, "Failed to get drvdata\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		goto exit_pdev_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	imx_dsp_set_data(priv->dsp_ipc, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	priv->dsp_ipc->ops = &imx8m_dsp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	/* DSP base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		base = mmio->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		size = resource_size(mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		dev_err(sdev->dev, "error: failed to get DSP base at idx 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		goto exit_pdev_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		dev_err(sdev->dev, "failed to ioremap base 0x%x size 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		goto exit_pdev_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	sdev->mmio_bar = SOF_FW_BLK_TYPE_IRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	res_node = of_parse_phandle(np, "memory-region", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (!res_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		dev_err(&pdev->dev, "failed to get memory region node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		goto exit_pdev_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	ret = of_address_to_resource(res_node, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	of_node_put(res_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		dev_err(&pdev->dev, "failed to get reserved region address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		goto exit_pdev_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, res.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 							  resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		dev_err(sdev->dev, "failed to ioremap mem 0x%x size 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		goto exit_pdev_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/* set default mailbox offset for FW ready message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	sdev->dsp_box.offset = MBOX_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) exit_pdev_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	platform_device_unregister(priv->ipc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int imx8m_remove(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct imx8m_priv *priv = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	platform_device_unregister(priv->ipc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* on i.MX8 there is 1 to 1 match between type and BAR idx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int imx8m_get_bar_index(struct snd_sof_dev *sdev, u32 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void imx8m_ipc_msg_data(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			       struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			       void *p, size_t sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	sof_mailbox_read(sdev, sdev->dsp_box.offset, p, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int imx8m_ipc_pcm_params(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 				struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 				const struct sof_ipc_pcm_params_reply *reply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static struct snd_soc_dai_driver imx8m_dai[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.name = "sai3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		.channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.channels_max = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		.channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		.channels_max = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* i.MX8 ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct snd_sof_dsp_ops sof_imx8m_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	/* probe and remove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.probe		= imx8m_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	.remove		= imx8m_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	/* DSP core boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.run		= imx8m_run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	/* Block IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.block_read	= sof_block_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.block_write	= sof_block_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	/* Module IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.read64	= sof_io_read64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	/* ipc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.send_msg	= imx8m_send_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.fw_ready	= sof_fw_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.get_mailbox_offset	= imx8m_get_mailbox_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.get_window_offset	= imx8m_get_window_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	.ipc_msg_data	= imx8m_ipc_msg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	.ipc_pcm_params	= imx8m_ipc_pcm_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	/* module loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.load_module	= snd_sof_parse_module_memcpy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.get_bar_index	= imx8m_get_bar_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	/* firmware loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.load_firmware	= snd_sof_load_firmware_memcpy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	/* Debug information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.dbg_dump = imx8_dump,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	/* Firmware ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.arch_ops = &sof_xtensa_arch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	/* DAI drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	.drv = imx8m_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.num_drv = ARRAY_SIZE(imx8m_dai),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.hw_info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) EXPORT_SYMBOL(sof_imx8m_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MODULE_LICENSE("Dual BSD/GPL");