^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright 2019 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Author: Daniel Baluta <daniel.baluta@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Hardware interface for audio DSP on i.MX8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/sof.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/sof/xtensa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/firmware/imx/ipc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/firmware/imx/dsp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/firmware/imx/svc/misc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <dt-bindings/firmware/imx/rsrc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "../ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "imx-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* DSP memories */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IRAM_OFFSET 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IRAM_SIZE (2 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRAM0_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRAM0_SIZE (32 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRAM1_OFFSET 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRAM1_SIZE (32 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SYSRAM_OFFSET 0x18000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SYSRAM_SIZE (256 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SYSROM_OFFSET 0x58000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SYSROM_SIZE (192 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RESET_VECTOR_VADDR 0x596f8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MBOX_OFFSET 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MBOX_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct imx8_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct snd_sof_dev *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* DSP IPC handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct imx_dsp_ipc *dsp_ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct platform_device *ipc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* System Controller IPC handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct imx_sc_ipc *sc_ipc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Power domain handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int num_domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct device **pd_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct device_link **link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void imx8_get_reply(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct snd_sof_ipc_msg *msg = sdev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct sof_ipc_reply reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (!msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) dev_warn(sdev->dev, "unexpected ipc interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* get reply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (reply.error < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) memcpy(msg->reply_data, &reply, sizeof(reply));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ret = reply.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* reply has correct size? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (reply.hdr.size != msg->reply_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) msg->reply_size, reply.hdr.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* read the message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (msg->reply_size > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) sof_mailbox_read(sdev, sdev->host_box.offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) msg->reply_data, msg->reply_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) msg->reply_error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int imx8_get_mailbox_offset(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return MBOX_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int imx8_get_window_offset(struct snd_sof_dev *sdev, u32 id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return MBOX_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void imx8_dsp_handle_reply(struct imx_dsp_ipc *ipc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct imx8_priv *priv = imx_dsp_get_data(ipc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) imx8_get_reply(priv->sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) snd_sof_ipc_reply(priv->sdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void imx8_dsp_handle_request(struct imx_dsp_ipc *ipc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct imx8_priv *priv = imx_dsp_get_data(ipc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 p; /* panic code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Read the message from the debug box. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, &p, sizeof(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Check to see if the message is a panic code (0x0dead***) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) snd_sof_dsp_panic(priv->sdev, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) snd_sof_ipc_msgs_rx(priv->sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static struct imx_dsp_ops dsp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .handle_reply = imx8_dsp_handle_reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .handle_request = imx8_dsp_handle_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int imx8_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct imx8_priv *priv = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) msg->msg_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) imx_dsp_ring_doorbell(priv->dsp_ipc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * DSP control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int imx8x_run(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct imx8_priv *dsp_priv = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) IMX_SC_C_OFS_SEL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dev_err(sdev->dev, "Error system address offset source select\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) IMX_SC_C_OFS_AUDIO, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dev_err(sdev->dev, "Error system address offset of AUDIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) IMX_SC_C_OFS_PERIPH, 0x5A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dev_err(sdev->dev, "Error system address offset of PERIPH %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) IMX_SC_C_OFS_IRQ, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_err(sdev->dev, "Error system address offset of IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) imx_sc_pm_cpu_start(dsp_priv->sc_ipc, IMX_SC_R_DSP, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) RESET_VECTOR_VADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int imx8_run(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct imx8_priv *dsp_priv = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) IMX_SC_C_OFS_SEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dev_err(sdev->dev, "Error system address offset source select\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) imx_sc_pm_cpu_start(dsp_priv->sc_ipc, IMX_SC_R_DSP, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) RESET_VECTOR_VADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int imx8_probe(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct platform_device *pdev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) container_of(sdev->dev, struct platform_device, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct device_node *res_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct resource *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct imx8_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 base, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) sdev->pdata->hw_pdata = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) priv->dev = sdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) priv->sdev = sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* power up device associated power domains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) priv->num_domains = of_count_phandle_with_args(np, "power-domains",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "#power-domain-cells");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (priv->num_domains < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_err(sdev->dev, "no power-domains property in %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return priv->num_domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) priv->pd_dev = devm_kmalloc_array(&pdev->dev, priv->num_domains,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) sizeof(*priv->pd_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (!priv->pd_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) priv->link = devm_kmalloc_array(&pdev->dev, priv->num_domains,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) sizeof(*priv->link), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!priv->link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) for (i = 0; i < priv->num_domains; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) priv->pd_dev[i] = dev_pm_domain_attach_by_id(&pdev->dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (IS_ERR(priv->pd_dev[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = PTR_ERR(priv->pd_dev[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) goto exit_unroll_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) priv->link[i] = device_link_add(&pdev->dev, priv->pd_dev[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) DL_FLAG_STATELESS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) DL_FLAG_PM_RUNTIME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) DL_FLAG_RPM_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!priv->link[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_pm_domain_detach(priv->pd_dev[i], false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) goto exit_unroll_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret = imx_scu_get_handle(&priv->sc_ipc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_err(sdev->dev, "Cannot obtain SCU handle (err = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) goto exit_unroll_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) priv->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PLATFORM_DEVID_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) pdev, sizeof(*pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (IS_ERR(priv->ipc_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = PTR_ERR(priv->ipc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) goto exit_unroll_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (!priv->dsp_ipc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* DSP IPC driver not probed yet, try later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_err(sdev->dev, "Failed to get drvdata\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) goto exit_pdev_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) imx_dsp_set_data(priv->dsp_ipc, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) priv->dsp_ipc->ops = &dsp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* DSP base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) base = mmio->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) size = resource_size(mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_err(sdev->dev, "error: failed to get DSP base at idx 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) goto exit_pdev_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev_err(sdev->dev, "failed to ioremap base 0x%x size 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) goto exit_pdev_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) sdev->mmio_bar = SOF_FW_BLK_TYPE_IRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) res_node = of_parse_phandle(np, "memory-region", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (!res_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_err(&pdev->dev, "failed to get memory region node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) goto exit_pdev_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ret = of_address_to_resource(res_node, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_err(&pdev->dev, "failed to get reserved region address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) goto exit_pdev_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, res.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dev_err(sdev->dev, "failed to ioremap mem 0x%x size 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) goto exit_pdev_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* set default mailbox offset for FW ready message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) sdev->dsp_box.offset = MBOX_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) exit_pdev_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) platform_device_unregister(priv->ipc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) exit_unroll_pm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) while (--i >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) device_link_del(priv->link[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_pm_domain_detach(priv->pd_dev[i], false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int imx8_remove(struct snd_sof_dev *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct imx8_priv *priv = sdev->pdata->hw_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) platform_device_unregister(priv->ipc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) for (i = 0; i < priv->num_domains; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) device_link_del(priv->link[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_pm_domain_detach(priv->pd_dev[i], false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* on i.MX8 there is 1 to 1 match between type and BAR idx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int imx8_get_bar_index(struct snd_sof_dev *sdev, u32 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static void imx8_ipc_msg_data(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) void *p, size_t sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) sof_mailbox_read(sdev, sdev->dsp_box.offset, p, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int imx8_ipc_pcm_params(struct snd_sof_dev *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) const struct sof_ipc_pcm_params_reply *reply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct snd_soc_dai_driver imx8_dai[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .name = "esai0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .name = "sai1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .channels_max = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .channels_max = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* i.MX8 ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct snd_sof_dsp_ops sof_imx8_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* probe and remove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .probe = imx8_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .remove = imx8_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* DSP core boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .run = imx8_run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Block IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .block_read = sof_block_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .block_write = sof_block_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Module IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .read64 = sof_io_read64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* ipc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .send_msg = imx8_send_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .fw_ready = sof_fw_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .get_mailbox_offset = imx8_get_mailbox_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .get_window_offset = imx8_get_window_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .ipc_msg_data = imx8_ipc_msg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .ipc_pcm_params = imx8_ipc_pcm_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* module loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .load_module = snd_sof_parse_module_memcpy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .get_bar_index = imx8_get_bar_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* firmware loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .load_firmware = snd_sof_load_firmware_memcpy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Debug information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .dbg_dump = imx8_dump,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* Firmware ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .arch_ops = &sof_xtensa_arch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* DAI drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .drv = imx8_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .num_drv = ARRAY_SIZE(imx8_dai),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* ALSA HW info flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .hw_info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) EXPORT_SYMBOL(sof_imx8_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* i.MX8X ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct snd_sof_dsp_ops sof_imx8x_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* probe and remove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .probe = imx8_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .remove = imx8_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* DSP core boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .run = imx8x_run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Block IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .block_read = sof_block_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .block_write = sof_block_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Module IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .read64 = sof_io_read64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* ipc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .send_msg = imx8_send_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .fw_ready = sof_fw_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .get_mailbox_offset = imx8_get_mailbox_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .get_window_offset = imx8_get_window_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .ipc_msg_data = imx8_ipc_msg_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .ipc_pcm_params = imx8_ipc_pcm_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* module loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .load_module = snd_sof_parse_module_memcpy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .get_bar_index = imx8_get_bar_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* firmware loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .load_firmware = snd_sof_load_firmware_memcpy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Debug information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .dbg_dump = imx8_dump,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Firmware ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .arch_ops = &sof_xtensa_arch_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* DAI drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .drv = imx8_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .num_drv = ARRAY_SIZE(imx8_dai),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* ALSA HW info flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .hw_info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) SNDRV_PCM_INFO_NO_PERIOD_WAKEUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) EXPORT_SYMBOL(sof_imx8x_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MODULE_LICENSE("Dual BSD/GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags