Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * arch/arm/mach-prima2/include/mach/sirfsoc_usp.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef _SIRF_USP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define _SIRF_USP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /* USP Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define USP_MODE1		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define USP_MODE2		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define USP_TX_FRAME_CTRL	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define USP_RX_FRAME_CTRL	0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define USP_TX_RX_ENABLE	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define USP_INT_ENABLE		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define USP_INT_STATUS		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define USP_PIN_IO_DATA		0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define USP_RISC_DSP_MODE	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define USP_AYSNC_PARAM_REG	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define USP_IRDA_X_MODE_DIV	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define USP_SM_CFG		0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define USP_TX_DMA_IO_CTRL	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define USP_TX_DMA_IO_LEN	0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define USP_TX_FIFO_CTRL	0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define USP_TX_FIFO_LEVEL_CHK	0x10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define USP_TX_FIFO_OP		0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define USP_TX_FIFO_STATUS	0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define USP_TX_FIFO_DATA	0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define USP_RX_DMA_IO_CTRL	0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define USP_RX_DMA_IO_LEN	0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define USP_RX_FIFO_CTRL	0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define USP_RX_FIFO_LEVEL_CHK	0x12C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define USP_RX_FIFO_OP		0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define USP_RX_FIFO_STATUS	0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define USP_RX_FIFO_DATA	0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* USP MODE register-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define USP_SYNC_MODE			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define USP_CLOCK_MODE_SLAVE		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define USP_LOOP_BACK_EN		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define USP_HPSIR_EN			0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define USP_ENDIAN_CTRL_LSBF		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define USP_EN				0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define USP_RXD_ACT_EDGE_FALLING	0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define USP_TXD_ACT_EDGE_FALLING	0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define USP_RFS_ACT_LEVEL_LOGIC1	0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define USP_TFS_ACT_LEVEL_LOGIC1	0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define USP_SCLK_IDLE_MODE_TOGGLE	0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define USP_SCLK_IDLE_LEVEL_LOGIC1	0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define USP_SCLK_PIN_MODE_IO	0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define USP_RFS_PIN_MODE_IO	0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define USP_TFS_PIN_MODE_IO	0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define USP_RXD_PIN_MODE_IO	0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define USP_TXD_PIN_MODE_IO	0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define USP_SCLK_IO_MODE_INPUT	0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define USP_RFS_IO_MODE_INPUT	0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define USP_TFS_IO_MODE_INPUT	0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define USP_RXD_IO_MODE_INPUT	0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define USP_TXD_IO_MODE_INPUT	0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define USP_IRDA_WIDTH_DIV_MASK	0x3FC00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define USP_IRDA_WIDTH_DIV_OFFSET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define USP_IRDA_IDLE_LEVEL_HIGH	0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define USP_TX_UFLOW_REPEAT_ZERO	0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define USP_TX_ENDIAN_MODE		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define USP_RX_ENDIAN_MODE		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /* USP Mode Register-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define USP_RXD_DELAY_LEN_MASK		0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define USP_RXD_DELAY_LEN_OFFSET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define USP_TXD_DELAY_LEN_MASK		0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define USP_TXD_DELAY_LEN_OFFSET	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define USP_ENA_CTRL_MODE		0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define USP_FRAME_CTRL_MODE		0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define USP_TFS_SOURCE_MODE             0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define USP_TFS_MS_MODE                 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define USP_CLK_DIVISOR_MASK		0x7FE00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define USP_CLK_DIVISOR_OFFSET		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define USP_TFS_CLK_SLAVE_MODE		(1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define USP_RFS_CLK_SLAVE_MODE		(1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define USP_IRDA_DATA_WIDTH		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /* USP Transmit Frame Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define USP_TXC_DATA_LEN_MASK		0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define USP_TXC_DATA_LEN_OFFSET		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define USP_TXC_SYNC_LEN_MASK		0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define USP_TXC_SYNC_LEN_OFFSET		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define USP_TXC_FRAME_LEN_MASK		0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define USP_TXC_FRAME_LEN_OFFSET	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define USP_TXC_SHIFTER_LEN_MASK	0x1F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define USP_TXC_SHIFTER_LEN_OFFSET	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define USP_TXC_SLAVE_CLK_SAMPLE	0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define USP_TXC_CLK_DIVISOR_MASK	0xC0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define USP_TXC_CLK_DIVISOR_OFFSET	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* USP Receive Frame Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define USP_RXC_DATA_LEN_MASK		0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define USP_RXC_DATA_LEN_OFFSET		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define USP_RXC_FRAME_LEN_MASK		0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define USP_RXC_FRAME_LEN_OFFSET	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define USP_RXC_SHIFTER_LEN_MASK	0x001F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define USP_RXC_SHIFTER_LEN_OFFSET	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define USP_START_EDGE_MODE	0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define USP_I2S_SYNC_CHG	0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define USP_RXC_CLK_DIVISOR_MASK	0x0F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define USP_RXC_CLK_DIVISOR_OFFSET	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define USP_SINGLE_SYNC_MODE		0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Tx - RX Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define USP_RX_ENA		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define USP_TX_ENA		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* USP Interrupt Enable and status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define USP_RX_DONE_INT			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define USP_TX_DONE_INT			0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define USP_RX_OFLOW_INT		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define USP_TX_UFLOW_INT		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define USP_RX_IO_DMA_INT		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define USP_TX_IO_DMA_INT		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define USP_RXFIFO_FULL_INT		0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define USP_TXFIFO_EMPTY_INT		0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define USP_RXFIFO_THD_INT		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define USP_TXFIFO_THD_INT		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define USP_UART_FRM_ERR_INT		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define USP_RX_TIMEOUT_INT		0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define USP_TX_ALLOUT_INT		0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define USP_RXD_BREAK_INT		0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* All possible TX interruots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define USP_TX_INTERRUPT		(USP_TX_DONE_INT|USP_TX_UFLOW_INT|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 					USP_TX_IO_DMA_INT|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 					USP_TXFIFO_EMPTY_INT|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 					USP_TXFIFO_THD_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* All possible RX interruots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define USP_RX_INTERRUPT		(USP_RX_DONE_INT|USP_RX_OFLOW_INT|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 					USP_RX_IO_DMA_INT|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 					USP_RXFIFO_FULL_INT|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 					USP_RXFIFO_THD_INT|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 					USP_RX_TIMEOUT_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define USP_INT_ALL        0x1FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* USP Pin I/O Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define USP_RFS_PIN_VALUE_MASK	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define USP_TFS_PIN_VALUE_MASK	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define USP_RXD_PIN_VALUE_MASK	0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define USP_TXD_PIN_VALUE_MASK	0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define USP_SCLK_PIN_VALUE_MASK	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* USP RISC/DSP Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define USP_RISC_DSP_SEL	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* USP ASYNC PARAMETER Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define USP_ASYNC_TIMEOUT_MASK	0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define USP_ASYNC_TIMEOUT_OFFSET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define USP_ASYNC_TIMEOUT(x)	(((x)&USP_ASYNC_TIMEOUT_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 				<<USP_ASYNC_TIMEOUT_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define USP_ASYNC_DIV2_MASK		0x003F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define USP_ASYNC_DIV2_OFFSET		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* USP TX DMA I/O MODE Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define USP_TX_MODE_IO			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* USP TX DMA I/O Length Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define USP_TX_DATA_LEN_MASK		0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define USP_TX_DATA_LEN_OFFSET		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* USP TX FIFO Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define USP_TX_FIFO_WIDTH_MASK		0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define USP_TX_FIFO_WIDTH_OFFSET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define USP_TX_FIFO_THD_MASK		0x000001FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define USP_TX_FIFO_THD_OFFSET		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* USP TX FIFO Level Check Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define USP_TX_FIFO_LEVEL_CHECK_MASK	0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define USP_TX_FIFO_SC_OFFSET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define USP_TX_FIFO_LC_OFFSET	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define USP_TX_FIFO_HC_OFFSET	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TX_FIFO_SC(x)		(((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				<< USP_TX_FIFO_SC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TX_FIFO_LC(x)		(((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				<< USP_TX_FIFO_LC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TX_FIFO_HC(x)		(((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 				<< USP_TX_FIFO_HC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* USP TX FIFO Operation Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define USP_TX_FIFO_RESET		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define USP_TX_FIFO_START		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* USP TX FIFO Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define USP_TX_FIFO_LEVEL_MASK		0x0000007F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define USP_TX_FIFO_LEVEL_OFFSET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define USP_TX_FIFO_FULL		0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define USP_TX_FIFO_EMPTY		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* USP TX FIFO Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define USP_TX_FIFO_DATA_MASK		0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define USP_TX_FIFO_DATA_OFFSET		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* USP RX DMA I/O MODE Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define USP_RX_MODE_IO			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define USP_RX_DMA_FLUSH		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* USP RX DMA I/O Length Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define USP_RX_DATA_LEN_MASK		0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define USP_RX_DATA_LEN_OFFSET		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* USP RX FIFO Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define USP_RX_FIFO_WIDTH_MASK		0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define USP_RX_FIFO_WIDTH_OFFSET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define USP_RX_FIFO_THD_MASK		0x000001FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define USP_RX_FIFO_THD_OFFSET		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* USP RX FIFO Level Check Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define USP_RX_FIFO_LEVEL_CHECK_MASK	0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define USP_RX_FIFO_SC_OFFSET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define USP_RX_FIFO_LC_OFFSET	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define USP_RX_FIFO_HC_OFFSET	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define RX_FIFO_SC(x)		(((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 				<< USP_RX_FIFO_SC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define RX_FIFO_LC(x)		(((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 				<< USP_RX_FIFO_LC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define RX_FIFO_HC(x)		(((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 				<< USP_RX_FIFO_HC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* USP RX FIFO Operation Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define USP_RX_FIFO_RESET		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define USP_RX_FIFO_START		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* USP RX FIFO Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define USP_RX_FIFO_LEVEL_MASK		0x0000007F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define USP_RX_FIFO_LEVEL_OFFSET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define USP_RX_FIFO_FULL		0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define USP_RX_FIFO_EMPTY		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* USP RX FIFO Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define USP_RX_FIFO_DATA_MASK		0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define USP_RX_FIFO_DATA_OFFSET		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  * When rx thd irq occur, sender just disable tx empty irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * Remaining data in tx fifo wil also be sent out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define USP_FIFO_SIZE			128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define USP_TX_FIFO_THRESHOLD		(USP_FIFO_SIZE/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define USP_RX_FIFO_THRESHOLD		(USP_FIFO_SIZE/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* FIFO_WIDTH for the USP_TX_FIFO_CTRL and USP_RX_FIFO_CTRL registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define USP_FIFO_WIDTH_BYTE  0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define USP_FIFO_WIDTH_WORD  0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define USP_FIFO_WIDTH_DWORD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define USP_ASYNC_DIV2          16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define USP_PLUGOUT_RETRY_CNT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define USP_TX_RX_FIFO_WIDTH_DWORD    2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SIRF_USP_DIV_MCLK	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SIRF_USP_I2S_TFS_SYNC	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SIRF_USP_I2S_RFS_SYNC	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #endif