^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SiRF USP in I2S/DSP mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "sirf-usp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct sirf_usp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 mode1_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 mode2_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int daifmt_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct snd_dmaengine_dai_dma_data playback_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct snd_dmaengine_dai_dma_data capture_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void sirf_usp_tx_enable(struct sirf_usp *usp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) regmap_update_bits(usp->regmap, USP_TX_FIFO_OP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) USP_TX_FIFO_RESET, USP_TX_FIFO_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) regmap_write(usp->regmap, USP_TX_FIFO_OP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) regmap_update_bits(usp->regmap, USP_TX_FIFO_OP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) USP_TX_FIFO_START, USP_TX_FIFO_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) USP_TX_ENA, USP_TX_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void sirf_usp_tx_disable(struct sirf_usp *usp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) USP_TX_ENA, ~USP_TX_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* FIFO stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) regmap_write(usp->regmap, USP_TX_FIFO_OP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void sirf_usp_rx_enable(struct sirf_usp *usp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) regmap_update_bits(usp->regmap, USP_RX_FIFO_OP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) USP_RX_FIFO_RESET, USP_RX_FIFO_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) regmap_write(usp->regmap, USP_RX_FIFO_OP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) regmap_update_bits(usp->regmap, USP_RX_FIFO_OP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) USP_RX_FIFO_START, USP_RX_FIFO_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) USP_RX_ENA, USP_RX_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void sirf_usp_rx_disable(struct sirf_usp *usp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) USP_RX_ENA, ~USP_RX_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* FIFO stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) regmap_write(usp->regmap, USP_RX_FIFO_OP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int sirf_usp_pcm_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) snd_soc_dai_init_dma_data(dai, &usp->playback_dma_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) &usp->capture_dma_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int sirf_usp_pcm_set_dai_fmt(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* set master/slave audio interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dev_err(dai->dev, "Only CBM and CFM supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) usp->daifmt_format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dev_err(dai->dev, "Only I2S and DSP_A format supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) usp->daifmt_format |= (fmt & SND_SOC_DAIFMT_INV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void sirf_usp_i2s_init(struct sirf_usp *usp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Configure RISC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) regmap_update_bits(usp->regmap, USP_RISC_DSP_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) USP_RISC_DSP_SEL, ~USP_RISC_DSP_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Configure DMA IO Length register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Set no limit, USP can receive data continuously until it is diabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) regmap_write(usp->regmap, USP_TX_DMA_IO_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) regmap_write(usp->regmap, USP_RX_DMA_IO_LEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Configure Mode2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) regmap_write(usp->regmap, USP_MODE2, (1 << USP_RXD_DELAY_LEN_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) (0 << USP_TXD_DELAY_LEN_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) USP_TFS_CLK_SLAVE_MODE | USP_RFS_CLK_SLAVE_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Configure Mode1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) regmap_write(usp->regmap, USP_MODE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) USP_SYNC_MODE | USP_EN | USP_TXD_ACT_EDGE_FALLING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) USP_RFS_ACT_LEVEL_LOGIC1 | USP_TFS_ACT_LEVEL_LOGIC1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) USP_TX_UFLOW_REPEAT_ZERO | USP_CLOCK_MODE_SLAVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Configure RX DMA IO Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) regmap_write(usp->regmap, USP_RX_DMA_IO_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Congiure RX FIFO Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) regmap_write(usp->regmap, USP_RX_FIFO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) (USP_RX_FIFO_THRESHOLD << USP_RX_FIFO_THD_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) (USP_TX_RX_FIFO_WIDTH_DWORD << USP_RX_FIFO_WIDTH_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Congiure RX FIFO Level Check register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) regmap_write(usp->regmap, USP_RX_FIFO_LEVEL_CHK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) RX_FIFO_SC(0x04) | RX_FIFO_LC(0x0E) | RX_FIFO_HC(0x1B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Configure TX DMA IO Control register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) regmap_write(usp->regmap, USP_TX_DMA_IO_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Configure TX FIFO Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) regmap_write(usp->regmap, USP_TX_FIFO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) (USP_TX_FIFO_THRESHOLD << USP_TX_FIFO_THD_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) (USP_TX_RX_FIFO_WIDTH_DWORD << USP_TX_FIFO_WIDTH_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Congiure TX FIFO Level Check register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) regmap_write(usp->regmap, USP_TX_FIFO_LEVEL_CHK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) TX_FIFO_SC(0x1B) | TX_FIFO_LC(0x0E) | TX_FIFO_HC(0x04));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int sirf_usp_pcm_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 data_len, frame_len, shifter_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) data_len = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) frame_len = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case SNDRV_PCM_FORMAT_S24_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) data_len = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) frame_len = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) case SNDRV_PCM_FORMAT_S24_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) data_len = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) frame_len = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dev_err(dai->dev, "Format unsupported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) shifter_len = data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) switch (usp->daifmt_format & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) USP_I2S_SYNC_CHG, USP_I2S_SYNC_CHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) USP_I2S_SYNC_CHG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) frame_len = data_len * params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) data_len = frame_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_err(dai->dev, "Only support I2S and DSP_A mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) switch (usp->daifmt_format & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) regmap_update_bits(usp->regmap, USP_MODE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) USP_RXD_ACT_EDGE_FALLING | USP_TXD_ACT_EDGE_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) USP_RXD_ACT_EDGE_FALLING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) regmap_update_bits(usp->regmap, USP_TX_FRAME_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) USP_TXC_DATA_LEN_MASK | USP_TXC_FRAME_LEN_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) | USP_TXC_SHIFTER_LEN_MASK | USP_TXC_SLAVE_CLK_SAMPLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ((data_len - 1) << USP_TXC_DATA_LEN_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) | ((frame_len - 1) << USP_TXC_FRAME_LEN_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) | ((shifter_len - 1) << USP_TXC_SHIFTER_LEN_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) | USP_TXC_SLAVE_CLK_SAMPLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) USP_RXC_DATA_LEN_MASK | USP_RXC_FRAME_LEN_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) | USP_RXC_SHIFTER_LEN_MASK | USP_SINGLE_SYNC_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ((data_len - 1) << USP_RXC_DATA_LEN_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) | ((frame_len - 1) << USP_RXC_FRAME_LEN_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) | ((shifter_len - 1) << USP_RXC_SHIFTER_LEN_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) | USP_SINGLE_SYNC_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int sirf_usp_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) sirf_usp_tx_enable(usp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) sirf_usp_rx_enable(usp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) sirf_usp_tx_disable(usp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) sirf_usp_rx_disable(usp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct snd_soc_dai_ops sirf_usp_pcm_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .trigger = sirf_usp_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .set_fmt = sirf_usp_pcm_set_dai_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .hw_params = sirf_usp_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct snd_soc_dai_driver sirf_usp_pcm_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .probe = sirf_usp_pcm_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .name = "sirf-usp-pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .stream_name = "SiRF USP PCM Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) SNDRV_PCM_FMTBIT_S24_3LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .stream_name = "SiRF USP PCM Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) SNDRV_PCM_FMTBIT_S24_3LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .ops = &sirf_usp_pcm_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int sirf_usp_pcm_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct sirf_usp *usp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) clk_disable_unprepare(usp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int sirf_usp_pcm_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct sirf_usp *usp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = clk_prepare_enable(usp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_err(dev, "clk_enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) sirf_usp_i2s_init(usp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int sirf_usp_pcm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct sirf_usp *usp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!pm_runtime_status_suspended(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) regmap_read(usp->regmap, USP_MODE1, &usp->mode1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) regmap_read(usp->regmap, USP_MODE2, &usp->mode2_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) sirf_usp_pcm_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int sirf_usp_pcm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct sirf_usp *usp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (!pm_runtime_status_suspended(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = sirf_usp_pcm_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) regmap_write(usp->regmap, USP_MODE1, usp->mode1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) regmap_write(usp->regmap, USP_MODE2, usp->mode2_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const struct snd_soc_component_driver sirf_usp_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .name = "sirf-usp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct regmap_config sirf_usp_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .max_register = USP_RX_FIFO_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .cache_type = REGCACHE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int sirf_usp_pcm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct sirf_usp *usp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) usp = devm_kzalloc(&pdev->dev, sizeof(struct sirf_usp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (!usp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) platform_set_drvdata(pdev, usp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) usp->regmap = devm_regmap_init_mmio(&pdev->dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) &sirf_usp_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (IS_ERR(usp->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return PTR_ERR(usp->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) usp->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (IS_ERR(usp->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev_err(&pdev->dev, "Get clock failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return PTR_ERR(usp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (!pm_runtime_enabled(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = sirf_usp_pcm_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = devm_snd_soc_register_component(&pdev->dev, &sirf_usp_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) &sirf_usp_pcm_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_err(&pdev->dev, "Register Audio SoC dai failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int sirf_usp_pcm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (!pm_runtime_enabled(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) sirf_usp_pcm_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static const struct of_device_id sirf_usp_pcm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { .compatible = "sirf,prima2-usp-pcm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MODULE_DEVICE_TABLE(of, sirf_usp_pcm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static const struct dev_pm_ops sirf_usp_pcm_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) SET_RUNTIME_PM_OPS(sirf_usp_pcm_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) sirf_usp_pcm_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) SET_SYSTEM_SLEEP_PM_OPS(sirf_usp_pcm_suspend, sirf_usp_pcm_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static struct platform_driver sirf_usp_pcm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .name = "sirf-usp-pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .of_match_table = sirf_usp_pcm_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .pm = &sirf_usp_pcm_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .probe = sirf_usp_pcm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .remove = sirf_usp_pcm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) module_platform_driver(sirf_usp_pcm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MODULE_DESCRIPTION("SiRF SoC USP PCM bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) MODULE_AUTHOR("RongJun Ying <Rongjun.Ying@csr.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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