Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Serial Sound Interface (I2S) support for SH7760/SH7780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // dont forget to set IPSEL/OMSEL register bits (in your board code) to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) // enable SSI output pins!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * LIMITATIONS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *	The SSI unit has only one physical data line, so full duplex is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *	impossible.  This can be remedied  on the  SH7760 by  using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *	other SSI unit for recording; however the SH7780 has only 1 SSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *	unit, and its pins are shared with the AC97 unit,  among others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * FEATURES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *	The SSI features "compressed mode": in this mode it continuously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *	streams PCM data over the I2S lines and uses LRCK as a handshake
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *	signal.  Can be used to send compressed data (AC3/DTS) to a DSP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *	The number of bits sent over the wire in a frame can be adjusted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *	and can be independent from the actual sample bit depth. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *	useful to support TDM mode codecs like the AD1939 which have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *	fixed TDM slot size, regardless of sample resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SSICR	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SSISR	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CR_DMAEN	(1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CR_CHNL_SHIFT	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CR_CHNL_MASK	(3 << CR_CHNL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CR_DWL_SHIFT	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CR_DWL_MASK	(7 << CR_DWL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CR_SWL_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CR_SWL_MASK	(7 << CR_SWL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CR_SCK_MASTER	(1 << 15)	/* bitclock master bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CR_SWS_MASTER	(1 << 14)	/* wordselect master bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CR_SCKP		(1 << 13)	/* I2Sclock polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CR_SWSP		(1 << 12)	/* LRCK polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CR_SPDP		(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CR_SDTA		(1 << 10)	/* i2s alignment (msb/lsb) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CR_PDTA		(1 << 9)	/* fifo data alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CR_DEL		(1 << 8)	/* delay data by 1 i2sclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CR_BREN		(1 << 7)	/* clock gating in burst mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CR_CKDIV_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CR_CKDIV_MASK	(7 << CR_CKDIV_SHIFT)	/* bitclock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CR_MUTE		(1 << 3)	/* SSI mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CR_CPEN		(1 << 2)	/* compressed mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CR_TRMD		(1 << 1)	/* transmit/receive select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CR_EN		(1 << 0)	/* enable SSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SSIREG(reg)	(*(unsigned long *)(ssi->mmio + (reg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) struct ssi_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	unsigned long mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	unsigned long sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	int inuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) } ssi_cpu_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #if defined(CONFIG_CPU_SUBTYPE_SH7760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		.mmio	= 0xFE680000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.mmio	= 0xFE690000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.mmio	= 0xFFE70000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #error "Unsupported SuperH SoC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  * track usage of the SSI; it is simplex-only so prevent attempts of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  * concurrent playback + capture. FIXME: any locking required?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static int ssi_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		       struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct ssi_priv *ssi = &ssi_cpu_data[dai->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (ssi->inuse) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		pr_debug("ssi: already in use!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		ssi->inuse = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void ssi_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			 struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct ssi_priv *ssi = &ssi_cpu_data[dai->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	ssi->inuse = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int ssi_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		       struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct ssi_priv *ssi = &ssi_cpu_data[dai->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		SSIREG(SSICR) |= CR_DMAEN | CR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		SSIREG(SSICR) &= ~(CR_DMAEN | CR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int ssi_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			 struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			 struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct ssi_priv *ssi = &ssi_cpu_data[dai->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	unsigned long ssicr = SSIREG(SSICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	unsigned int bits, channels, swl, recv, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	bits = params->msbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	recv = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	pr_debug("ssi_hw_params() enter\nssicr was    %08lx\n", ssicr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	pr_debug("bits: %u channels: %u\n", bits, channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	ssicr &= ~(CR_TRMD | CR_CHNL_MASK | CR_DWL_MASK | CR_PDTA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		   CR_SWL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	/* direction (send/receive) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (!recv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		ssicr |= CR_TRMD;	/* transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	/* channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if ((channels < 2) || (channels > 8) || (channels & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		pr_debug("ssi: invalid number of channels\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	ssicr |= ((channels >> 1) - 1) << CR_CHNL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/* DATA WORD LENGTH (DWL): databits in audio sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	switch (bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	case 32: ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	case 24: ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	case 22: ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	case 20: ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	case 18: ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	case 16: ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		 ssicr |= i << CR_DWL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	case 8:	 break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		pr_debug("ssi: invalid sample width\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	 * SYSTEM WORD LENGTH: size in bits of half a frame over the I2S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	 * wires. This is usually bits_per_sample x channels/2;  i.e. in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	 * Stereo mode  the SWL equals DWL.  SWL can  be bigger than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	 * product of (channels_per_slot x samplebits), e.g.  for codecs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	 * like the AD1939 which  only accept 32bit wide TDM slots.  For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	 * "standard" I2S operation we set SWL = chans / 2 * DWL here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 * Waiting for ASoC to get TDM support ;-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if ((bits > 16) && (bits <= 24)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		bits = 24;	/* these are padded by the SSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		/*ssicr |= CR_PDTA;*/ /* cpu/data endianness ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	swl = (bits * channels) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	switch (swl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	case 256: ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	case 128: ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	case 64:  ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	case 48:  ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	case 32:  ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	case 16:  ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		  ssicr |= i << CR_SWL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	case 8:   break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		pr_debug("ssi: invalid system word length computed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	SSIREG(SSICR) = ssicr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	pr_debug("ssi_hw_params() leave\nssicr is now %08lx\n", ssicr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int ssi_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			  unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct ssi_priv *ssi = &ssi_cpu_data[cpu_dai->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	ssi->sysclk = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  * This divider is used to generate the SSI_SCK (I2S bitclock) from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  * clock at the HAC_BIT_CLK ("oversampling clock") pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int ssi_set_clkdiv(struct snd_soc_dai *dai, int did, int div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct ssi_priv *ssi = &ssi_cpu_data[dai->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	unsigned long ssicr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	ssicr = SSIREG(SSICR) & ~CR_CKDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	switch (div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	case 16: ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	case 8:  ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	case 4:  ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	case 2:  ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		 SSIREG(SSICR) = ssicr | (i << CR_CKDIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	case 1:  break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		pr_debug("ssi: invalid sck divider %d\n", div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int ssi_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct ssi_priv *ssi = &ssi_cpu_data[dai->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	unsigned long ssicr = SSIREG(SSICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	pr_debug("ssi_set_fmt()\nssicr was    0x%08lx\n", ssicr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	ssicr &= ~(CR_DEL | CR_PDTA | CR_BREN | CR_SWSP | CR_SCKP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		   CR_SWS_MASTER | CR_SCK_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	case SND_SOC_DAIFMT_RIGHT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		ssicr |= CR_DEL | CR_PDTA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		ssicr |= CR_DEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		pr_debug("ssi: unsupported format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	case SND_SOC_DAIFMT_CONT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	case SND_SOC_DAIFMT_GATED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		ssicr |= CR_BREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		ssicr |= CR_SCKP;	/* sample data at low clkedge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		ssicr |= CR_SCKP | CR_SWSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		ssicr |= CR_SWSP;	/* word select starts low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		pr_debug("ssi: invalid inversion\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	case SND_SOC_DAIFMT_CBS_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		ssicr |= CR_SCK_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	case SND_SOC_DAIFMT_CBM_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		ssicr |= CR_SWS_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		ssicr |= CR_SWS_MASTER | CR_SCK_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		pr_debug("ssi: invalid master/secondary configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	SSIREG(SSICR) = ssicr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	pr_debug("ssi_set_fmt() leave\nssicr is now 0x%08lx\n", ssicr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* the SSI depends on an external clocksource (at HAC_BIT_CLK) even in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)  * Master mode,  so really this is board specific;  the SSI can do any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)  * rate with the right bitclk and divider settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define SSI_RATES	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	SNDRV_PCM_RATE_8000_192000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* the SSI can do 8-32 bit samples, with 8 possible channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SSI_FMTS	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	(SNDRV_PCM_FMTBIT_S8      | SNDRV_PCM_FMTBIT_U8      |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	 SNDRV_PCM_FMTBIT_S16_LE  | SNDRV_PCM_FMTBIT_U16_LE  |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_U24_3LE |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	 SNDRV_PCM_FMTBIT_S32_LE  | SNDRV_PCM_FMTBIT_U32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct snd_soc_dai_ops ssi_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	.startup	= ssi_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	.shutdown	= ssi_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	.trigger	= ssi_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.hw_params	= ssi_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.set_sysclk	= ssi_set_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	.set_clkdiv	= ssi_set_clkdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	.set_fmt	= ssi_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static struct snd_soc_dai_driver sh4_ssi_dai[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.name			= "ssi-dai.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.rates		= SSI_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		.formats	= SSI_FMTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		.channels_min	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		.channels_max	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	.capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		.rates		= SSI_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		.formats	= SSI_FMTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		.channels_min	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.channels_max	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	.ops = &ssi_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #ifdef CONFIG_CPU_SUBTYPE_SH7760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	.name			= "ssi-dai.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	.playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		.rates		= SSI_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		.formats	= SSI_FMTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		.channels_min	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		.channels_max	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	.capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		.rates		= SSI_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		.formats	= SSI_FMTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		.channels_min	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		.channels_max	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	.ops = &ssi_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const struct snd_soc_component_driver sh4_ssi_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	.name		= "sh4-ssi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int sh4_soc_dai_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	return devm_snd_soc_register_component(&pdev->dev, &sh4_ssi_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 					       sh4_ssi_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 					       ARRAY_SIZE(sh4_ssi_dai));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static struct platform_driver sh4_ssi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 			.name = "sh4-ssi-dai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	.probe = sh4_soc_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) module_platform_driver(sh4_ssi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MODULE_DESCRIPTION("SuperH onchip SSI (I2S) audio driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MODULE_AUTHOR("Manuel Lauss <mano@roarinelk.homelinux.net>");