Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // siu_pcm.c - ALSA driver for Renesas SH7343, SH7722 SIU peripheral.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // Copyright (C) 2006 Carlos Munoz <carlos@kenati.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/siu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "siu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DRV_NAME "siu-i2s"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define GET_MAX_PERIODS(buf_bytes, period_bytes) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 				((buf_bytes) / (period_bytes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PERIOD_OFFSET(buf_addr, period_num, period_bytes) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 				((buf_addr) + ((period_num) * (period_bytes)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define RWF_STM_RD		0x01		/* Read in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define RWF_STM_WT		0x02		/* Write in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) struct siu_port *siu_ports[SIU_PORT_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* transfersize is number of u32 dma transfers per period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static int siu_pcm_stmwrite_stop(struct siu_port *port_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct siu_info *info = siu_i2s_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u32 __iomem *base = info->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct siu_stream *siu_stream = &port_info->playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u32 stfifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	if (!siu_stream->rw_flg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	/* output FIFO disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	stfifo = siu_read32(base + SIU_STFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	siu_write32(base + SIU_STFIFO, stfifo & ~0x0c180c18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	pr_debug("%s: STFIFO %x -> %x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		 stfifo, stfifo & ~0x0c180c18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	/* during stmwrite clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	siu_stream->rw_flg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static int siu_pcm_stmwrite_start(struct siu_port *port_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct siu_stream *siu_stream = &port_info->playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	if (siu_stream->rw_flg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	/* Current period in buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	port_info->playback.cur_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	/* during stmwrite flag set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	siu_stream->rw_flg = RWF_STM_WT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	/* DMA transfer start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	queue_work(system_highpri_wq, &siu_stream->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static void siu_dma_tx_complete(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct siu_stream *siu_stream = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (!siu_stream->rw_flg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/* Update completed period count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	if (++siu_stream->cur_period >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	    GET_MAX_PERIODS(siu_stream->buf_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			    siu_stream->period_bytes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		siu_stream->cur_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	pr_debug("%s: done period #%d (%u/%u bytes), cookie %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		__func__, siu_stream->cur_period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		siu_stream->cur_period * siu_stream->period_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		siu_stream->buf_bytes, siu_stream->cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	queue_work(system_highpri_wq, &siu_stream->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	/* Notify alsa: a period is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	snd_pcm_period_elapsed(siu_stream->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int siu_pcm_wr_set(struct siu_port *port_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			  dma_addr_t buff, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct siu_info *info = siu_i2s_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	u32 __iomem *base = info->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct siu_stream *siu_stream = &port_info->playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct snd_pcm_substream *substream = siu_stream->substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct device *dev = substream->pcm->card->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct scatterlist sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	u32 stfifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	sg_init_table(&sg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	sg_set_page(&sg, pfn_to_page(PFN_DOWN(buff)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		    size, offset_in_page(buff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	sg_dma_len(&sg) = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	sg_dma_address(&sg) = buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	desc = dmaengine_prep_slave_sg(siu_stream->chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		&sg, 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		dev_err(dev, "Failed to allocate a dma descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	desc->callback = siu_dma_tx_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	desc->callback_param = siu_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	cookie = dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (cookie < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		dev_err(dev, "Failed to submit a dma transfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		return cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	siu_stream->tx_desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	siu_stream->cookie = cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	dma_async_issue_pending(siu_stream->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/* only output FIFO enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	stfifo = siu_read32(base + SIU_STFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	siu_write32(base + SIU_STFIFO, stfifo | (port_info->stfifo & 0x0c180c18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	dev_dbg(dev, "%s: STFIFO %x -> %x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		stfifo, stfifo | (port_info->stfifo & 0x0c180c18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int siu_pcm_rd_set(struct siu_port *port_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			  dma_addr_t buff, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct siu_info *info = siu_i2s_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u32 __iomem *base = info->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct siu_stream *siu_stream = &port_info->capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	struct snd_pcm_substream *substream = siu_stream->substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct device *dev = substream->pcm->card->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	struct scatterlist sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	u32 stfifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	dev_dbg(dev, "%s: %u@%llx\n", __func__, size, (unsigned long long)buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	sg_init_table(&sg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	sg_set_page(&sg, pfn_to_page(PFN_DOWN(buff)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		    size, offset_in_page(buff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	sg_dma_len(&sg) = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	sg_dma_address(&sg) = buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	desc = dmaengine_prep_slave_sg(siu_stream->chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		&sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		dev_err(dev, "Failed to allocate dma descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	desc->callback = siu_dma_tx_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	desc->callback_param = siu_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	cookie = dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (cookie < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		dev_err(dev, "Failed to submit dma descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	siu_stream->tx_desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	siu_stream->cookie = cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	dma_async_issue_pending(siu_stream->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* only input FIFO enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	stfifo = siu_read32(base + SIU_STFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	siu_write32(base + SIU_STFIFO, siu_read32(base + SIU_STFIFO) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		    (port_info->stfifo & 0x13071307));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	dev_dbg(dev, "%s: STFIFO %x -> %x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		stfifo, stfifo | (port_info->stfifo & 0x13071307));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void siu_io_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct siu_stream *siu_stream = container_of(work, struct siu_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 						     work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	struct snd_pcm_substream *substream = siu_stream->substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct device *dev = substream->pcm->card->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct snd_pcm_runtime *rt = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct siu_port *port_info = siu_port_info(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	dev_dbg(dev, "%s: flags %x\n", __func__, siu_stream->rw_flg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (!siu_stream->rw_flg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		dev_dbg(dev, "%s: stream inactive\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		dma_addr_t buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		size_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		u8 *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		buff = (dma_addr_t)PERIOD_OFFSET(rt->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 						siu_stream->cur_period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 						siu_stream->period_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		virt = PERIOD_OFFSET(rt->dma_area,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 				     siu_stream->cur_period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 				     siu_stream->period_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		count = siu_stream->period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		/* DMA transfer start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		siu_pcm_rd_set(port_info, buff, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		siu_pcm_wr_set(port_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			       (dma_addr_t)PERIOD_OFFSET(rt->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 						siu_stream->cur_period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 						siu_stream->period_bytes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			       siu_stream->period_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int siu_pcm_stmread_start(struct siu_port *port_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct siu_stream *siu_stream = &port_info->capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (siu_stream->xfer_cnt > 0x1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (siu_stream->rw_flg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/* Current period in buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	siu_stream->cur_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	/* during stmread flag set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	siu_stream->rw_flg = RWF_STM_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	queue_work(system_highpri_wq, &siu_stream->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int siu_pcm_stmread_stop(struct siu_port *port_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct siu_info *info = siu_i2s_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	u32 __iomem *base = info->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	struct siu_stream *siu_stream = &port_info->capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct device *dev = siu_stream->substream->pcm->card->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	u32 stfifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (!siu_stream->rw_flg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	/* input FIFO disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	stfifo = siu_read32(base + SIU_STFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	siu_write32(base + SIU_STFIFO, stfifo & ~0x13071307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	dev_dbg(dev, "%s: STFIFO %x -> %x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		stfifo, stfifo & ~0x13071307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	/* during stmread flag clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	siu_stream->rw_flg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static bool filter(struct dma_chan *chan, void *secondary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	struct sh_dmae_slave *param = secondary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	pr_debug("%s: secondary ID %d\n", __func__, param->shdma_slave.slave_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	chan->private = &param->shdma_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int siu_pcm_open(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	/* Playback / Capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	struct siu_platform *pdata = component->dev->platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	struct siu_info *info = siu_i2s_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	struct siu_port *port_info = siu_port_info(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	struct siu_stream *siu_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	u32 port = info->port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	struct device *dev = ss->pcm->card->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	struct sh_dmae_slave *param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	dma_cap_set(DMA_SLAVE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	dev_dbg(dev, "%s, port=%d@%p\n", __func__, port, port_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		siu_stream = &port_info->playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		param = &siu_stream->param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		param->shdma_slave.slave_id = port ? pdata->dma_slave_tx_b :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			pdata->dma_slave_tx_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		siu_stream = &port_info->capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		param = &siu_stream->param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		param->shdma_slave.slave_id = port ? pdata->dma_slave_rx_b :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			pdata->dma_slave_rx_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	/* Get DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	siu_stream->chan = dma_request_channel(mask, filter, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (!siu_stream->chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		dev_err(dev, "DMA channel allocation failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	siu_stream->substream = ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int siu_pcm_close(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			 struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	struct siu_info *info = siu_i2s_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	struct device *dev = ss->pcm->card->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	struct siu_port *port_info = siu_port_info(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	struct siu_stream *siu_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	dev_dbg(dev, "%s: port=%d\n", __func__, info->port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		siu_stream = &port_info->playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		siu_stream = &port_info->capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	dma_release_channel(siu_stream->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	siu_stream->chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	siu_stream->substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int siu_pcm_prepare(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			   struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	struct siu_info *info = siu_i2s_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	struct siu_port *port_info = siu_port_info(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	struct device *dev = ss->pcm->card->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	struct snd_pcm_runtime 	*rt = ss->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	struct siu_stream *siu_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	snd_pcm_sframes_t xfer_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		siu_stream = &port_info->playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		siu_stream = &port_info->capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	rt = siu_stream->substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	siu_stream->buf_bytes = snd_pcm_lib_buffer_bytes(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	siu_stream->period_bytes = snd_pcm_lib_period_bytes(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	dev_dbg(dev, "%s: port=%d, %d channels, period=%u bytes\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		info->port_id, rt->channels, siu_stream->period_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	/* We only support buffers that are multiples of the period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	if (siu_stream->buf_bytes % siu_stream->period_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		dev_err(dev, "%s() - buffer=%d not multiple of period=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		       __func__, siu_stream->buf_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		       siu_stream->period_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	xfer_cnt = bytes_to_frames(rt, siu_stream->period_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	if (!xfer_cnt || xfer_cnt > 0x1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	siu_stream->format = rt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	siu_stream->xfer_cnt = xfer_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	dev_dbg(dev, "port=%d buf=%lx buf_bytes=%d period_bytes=%d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		"format=%d channels=%d xfer_cnt=%d\n", info->port_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		(unsigned long)rt->dma_addr, siu_stream->buf_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		siu_stream->period_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		siu_stream->format, rt->channels, (int)xfer_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int siu_pcm_trigger(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 			   struct snd_pcm_substream *ss, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	struct siu_info *info = siu_i2s_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	struct device *dev = ss->pcm->card->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	struct siu_port *port_info = siu_port_info(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	dev_dbg(dev, "%s: port=%d@%p, cmd=%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		info->port_id, port_info, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 			ret = siu_pcm_stmwrite_start(port_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 			ret = siu_pcm_stmread_start(port_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 			dev_warn(dev, "%s: start failed on port=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 				 __func__, info->port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 			siu_pcm_stmwrite_stop(port_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 			siu_pcm_stmread_stop(port_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		dev_err(dev, "%s() unsupported cmd=%d\n", __func__, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)  * So far only resolution of one period is supported, subject to extending the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)  * dmangine API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) siu_pcm_pointer_dma(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		    struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	struct device *dev = ss->pcm->card->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	struct siu_info *info = siu_i2s_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	u32 __iomem *base = info->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	struct siu_port *port_info = siu_port_info(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	struct snd_pcm_runtime *rt = ss->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	size_t ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	struct siu_stream *siu_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		siu_stream = &port_info->playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		siu_stream = &port_info->capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	 * ptr is the offset into the buffer where the dma is currently at. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	 * check if the dma buffer has just wrapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	ptr = PERIOD_OFFSET(rt->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 			    siu_stream->cur_period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 			    siu_stream->period_bytes) - rt->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		"%s: port=%d, events %x, FSTS %x, xferred %u/%u, cookie %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		__func__, info->port_id, siu_read32(base + SIU_EVNTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		siu_read32(base + SIU_SBFSTS), ptr, siu_stream->buf_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		siu_stream->cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	if (ptr >= siu_stream->buf_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 		ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	return bytes_to_frames(ss->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int siu_pcm_new(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 		       struct snd_soc_pcm_runtime *rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	/* card->dev == socdev->dev, see snd_soc_new_pcms() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	struct snd_card *card = rtd->card->snd_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	struct snd_pcm *pcm = rtd->pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	struct siu_info *info = siu_i2s_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	struct platform_device *pdev = to_platform_device(card->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	/* pdev->id selects between SIUA and SIUB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	if (pdev->id < 0 || pdev->id >= SIU_PORT_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	info->port_id = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	 * While the siu has 2 ports, only one port can be on at a time (only 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	 * SPB). So far all the boards using the siu had only one of the ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	 * wired to a codec. To simplify things, we only register one port with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	 * alsa. In case both ports are needed, it should be changed here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	for (i = pdev->id; i < pdev->id + 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		struct siu_port **port_info = &siu_ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 		ret = siu_init_port(i, port_info, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		snd_pcm_set_managed_buffer_all(pcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 				SNDRV_DMA_TYPE_DEV, card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 				SIU_BUFFER_BYTES_MAX, SIU_BUFFER_BYTES_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		(*port_info)->pcm = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		/* IO works */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 		INIT_WORK(&(*port_info)->playback.work, siu_io_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		INIT_WORK(&(*port_info)->capture.work, siu_io_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	dev_info(card->dev, "SuperH SIU driver initialized.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static void siu_pcm_free(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 			 struct snd_pcm *pcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	struct platform_device *pdev = to_platform_device(pcm->card->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	struct siu_port *port_info = siu_ports[pdev->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	cancel_work_sync(&port_info->capture.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	cancel_work_sync(&port_info->playback.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	siu_free_port(port_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	dev_dbg(pcm->card->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) const struct snd_soc_component_driver siu_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	.open		= siu_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	.close		= siu_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	.prepare	= siu_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	.trigger	= siu_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	.pointer	= siu_pcm_pointer_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	.pcm_construct	= siu_pcm_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	.pcm_destruct	= siu_pcm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) EXPORT_SYMBOL_GPL(siu_component);