^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // siu.h - ALSA SoC driver for Renesas SH7343, SH7722 SIU peripheral.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright (C) 2006 Carlos Munoz <carlos@kenati.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef SIU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define SIU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Common kernel and user-space firmware-building defines and types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define YRAM0_SIZE (0x0040 / 4) /* 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define YRAM1_SIZE (0x0080 / 4) /* 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define YRAM2_SIZE (0x0040 / 4) /* 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define YRAM3_SIZE (0x0080 / 4) /* 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define YRAM4_SIZE (0x0080 / 4) /* 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define YRAM_DEF_SIZE (YRAM0_SIZE + YRAM1_SIZE + YRAM2_SIZE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) YRAM3_SIZE + YRAM4_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define YRAM_FIR_SIZE (0x0400 / 4) /* 256 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define YRAM_IIR_SIZE (0x0200 / 4) /* 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define XRAM0_SIZE (0x0400 / 4) /* 256 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define XRAM1_SIZE (0x0200 / 4) /* 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define XRAM2_SIZE (0x0200 / 4) /* 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* PRAM program array size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PRAM0_SIZE (0x0100 / 4) /* 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PRAM1_SIZE ((0x2000 - 0x0100) / 4) /* 1984 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct siu_spb_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) __u32 ab1a; /* input FIFO address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) __u32 ab0a; /* output FIFO address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) __u32 dir; /* 0=the ather except CPUOUTPUT, 1=CPUINPUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) __u32 event; /* SPB program starting conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) __u32 stfifo; /* STFIFO register setting value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) __u32 trdat; /* TRDAT register setting value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct siu_firmware {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) __u32 yram_fir_coeff[YRAM_FIR_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) __u32 pram0[PRAM0_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __u32 pram1[PRAM1_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) __u32 yram0[YRAM0_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __u32 yram1[YRAM1_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __u32 yram2[YRAM2_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __u32 yram3[YRAM3_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) __u32 yram4[YRAM4_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __u32 spbpar_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct siu_spb_param spbpar[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/sh_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SIU_PERIOD_BYTES_MAX 8192 /* DMA transfer/period size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SIU_PERIOD_BYTES_MIN 256 /* DMA transfer/period size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SIU_PERIODS_MAX 64 /* Max periods in buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SIU_PERIODS_MIN 4 /* Min periods in buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SIU_BUFFER_BYTES_MAX (SIU_PERIOD_BYTES_MAX * SIU_PERIODS_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* SIU ports: only one can be used at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SIU_PORT_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SIU_PORT_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SIU_PORT_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* SIU clock configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) SIU_CLKA_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) SIU_CLKA_EXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SIU_CLKB_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) SIU_CLKB_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct siu_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 __iomem *pram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 __iomem *xram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 __iomem *yram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct siu_firmware fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct siu_stream {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) snd_pcm_format_t format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) size_t buf_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) size_t period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int cur_period; /* Period currently in dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) snd_pcm_sframes_t xfer_cnt; /* Number of frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 rw_flg; /* transfer status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* DMA status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct dma_chan *chan; /* DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct dma_async_tx_descriptor *tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct sh_dmae_slave param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct siu_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long play_cap; /* Used to track full duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct siu_stream playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct siu_stream capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 stfifo; /* STFIFO value from firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 trdat; /* TRDAT value from firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) extern struct siu_port *siu_ports[SIU_PORT_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline struct siu_port *siu_port_info(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct platform_device *pdev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) to_platform_device(substream->pcm->card->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return siu_ports[pdev->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static inline void siu_write32(u32 __iomem *addr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __raw_writel(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static inline u32 siu_read32(u32 __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return __raw_readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* SIU registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SIU_IFCTL (0x000 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SIU_SRCTL (0x004 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SIU_SFORM (0x008 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SIU_CKCTL (0x00c / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SIU_TRDAT (0x010 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SIU_STFIFO (0x014 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SIU_DPAK (0x01c / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SIU_CKREV (0x020 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SIU_EVNTC (0x028 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SIU_SBCTL (0x040 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SIU_SBPSET (0x044 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SIU_SBFSTS (0x068 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SIU_SBDVCA (0x06c / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SIU_SBDVCB (0x070 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SIU_SBACTIV (0x074 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SIU_DMAIA (0x090 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SIU_DMAIB (0x094 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SIU_DMAOA (0x098 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SIU_DMAOB (0x09c / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SIU_DMAML (0x0a0 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SIU_SPSTS (0x0cc / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SIU_SPCTL (0x0d0 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SIU_BRGASEL (0x100 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SIU_BRRA (0x104 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SIU_BRGBSEL (0x108 / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SIU_BRRB (0x10c / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) extern const struct snd_soc_component_driver siu_component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) extern struct siu_info *siu_i2s_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int siu_init_port(int port, struct siu_port **port_info, struct snd_card *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) void siu_free_port(struct siu_port *port_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif /* SIU_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags