^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Fifo-attached Serial Interface (FSI) support for SH7724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2009 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Kuninori Morimoto <morimoto.kuninori@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Based on ssi.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sh_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/sh_fsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* PortA/PortB register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REG_DO_FMT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_DOFF_CTL 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REG_DOFF_ST 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_DI_FMT 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REG_DIFF_CTL 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_DIFF_ST 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_CKG1 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_CKG2 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_DIDT 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_DODT 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_MUTE_ST 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REG_OUT_DMAC 0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define REG_OUT_SEL 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_IN_DMAC 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* master register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MST_CLK_RST 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MST_SOFT_RST 0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MST_FIFO_SZ 0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* core register (depend on FSI version) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define A_MST_CTLR 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define B_MST_CTLR 0x01A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CPU_INT_ST 0x01F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CPU_IEMSK 0x01F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CPU_IMSK 0x01FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define INT_ST 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IEMSK 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMSK 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* DO_FMT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* DI_FMT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CR_BWS_MASK (0x3 << 20) /* FSI2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CR_BWS_24 (0x0 << 20) /* FSI2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CR_BWS_16 (0x1 << 20) /* FSI2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CR_BWS_20 (0x2 << 20) /* FSI2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CR_MONO (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CR_MONO_D (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CR_PCM (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CR_I2S (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CR_TDM (0x4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CR_TDM_D (0x5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* OUT_DMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* IN_DMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define VDMD_MASK (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define VDMD_FRONT (0x0 << 4) /* Package in front */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define VDMD_BACK (0x1 << 4) /* Package in back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DMA_ON (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* DOFF_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* DIFF_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IRQ_HALF 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define FIFO_CLR 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* DOFF_ST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ERR_OVER 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ERR_UNDER 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ST_ERR (ERR_OVER | ERR_UNDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* CKG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ACKMD_MASK 0x00007000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define BPFMD_MASK 0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DIMD (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DOMD (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* A/B MST_CTLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BP (1 << 4) /* Fix the signal of Biphase output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SE (1 << 0) /* Fix the master clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* CLK_RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CRB (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CRA (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* IO SHIFT / MACRO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BI_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BO_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AI_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AO_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AB_IO(param, shift) (param << shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* SOFT_RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PBSR (1 << 12) /* Port B Software Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PASR (1 << 8) /* Port A Software Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IR (1 << 4) /* Interrupt Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define FSISR (1 << 0) /* Software Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* OUT_SEL (FSI2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* 1: Biphase and serial */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* FIFO_SZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define FIFO_SZ_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define FSI_RATES SNDRV_PCM_RATE_8000_96000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * bus options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * 0x000000BA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * A : sample widtht 16bit setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * B : sample widtht 24bit setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SHIFT_16DATA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SHIFT_24DATA 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PACKAGE_24BITBUS_BACK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PACKAGE_24BITBUS_FRONT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PACKAGE_16BITBUS_STREAM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * FSI driver use below type name for variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * xxx_num : number of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * xxx_pos : position of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * xxx_capa : capacity of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * period/frame/sample image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * ex) PCM (2ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * period pos period pos
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * [n] [n + 1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * |<-------------------- period--------------------->|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * ==|============================================ ... =|==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * ||<----- frame ----->|<------ frame ----->| ... |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * |+--------------------+--------------------+- ... |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * |+--------------------+--------------------+- ... |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * ==|============================================ ... =|==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * FSI FIFO image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * | [ sample ] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * | [ sample ] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * | [ sample ] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * | [ sample ] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * --> go to codecs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * FSI clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * FSIxCLK [CPG] (ick) -------> |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * |-> FSI_DIV (div)-> FSI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * FSIxCK [external] (xck) ---> |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct fsi_stream_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct fsi_stream {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * these are initialized by fsi_stream_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int fifo_sample_capa; /* sample capacity of FSI FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int buff_sample_capa; /* sample capacity of ALSA buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int buff_sample_pos; /* sample position of ALSA buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int period_samples; /* sample number / 1 period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int period_pos; /* current period position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int sample_width; /* sample width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int uerr_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int oerr_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * bus options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 bus_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * thse are initialized by fsi_handler_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct fsi_stream_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct fsi_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * these are for DMAEngine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int dma_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct fsi_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* see [FSI clock] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct clk *own;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct clk *xck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct clk *ick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct clk *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int (*set_rate)(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct fsi_priv *fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct fsi_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) phys_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct fsi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct fsi_stream playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct fsi_stream capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct fsi_clk clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int chan_num:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int clk_master:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned int clk_cpg:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int spdif:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int enable_stream:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned int bit_clk_inv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int lr_clk_inv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct fsi_stream_handler {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int (*init)(struct fsi_priv *fsi, struct fsi_stream *io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define fsi_stream_handler_call(io, func, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) (!(io) ? -ENODEV : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) !((io)->handler->func) ? 0 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) (io)->handler->func(args))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct fsi_core {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 int_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 iemsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 imsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 a_mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 b_mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct fsi_master {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct fsi_priv fsia;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct fsi_priv fsib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) const struct fsi_core *core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static inline int fsi_stream_is_play(struct fsi_priv *fsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct fsi_stream *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return &fsi->playback == io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * basic read write function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void __fsi_reg_write(u32 __iomem *reg, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* valid data area is 24bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) data &= 0x00ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) __raw_writel(data, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static u32 __fsi_reg_read(u32 __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return __raw_readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 val = __fsi_reg_read(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) val |= data & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) __fsi_reg_write(reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define fsi_reg_write(p, r, d)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) __fsi_reg_write((p->base + REG_##r), d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define fsi_reg_read(p, r)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) __fsi_reg_read((p->base + REG_##r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define fsi_reg_mask_set(p, r, m, d)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) __fsi_reg_mask_set((p->base + REG_##r), m, d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) spin_lock_irqsave(&master->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ret = __fsi_reg_read(master->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) spin_unlock_irqrestore(&master->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static void _fsi_master_mask_set(struct fsi_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 reg, u32 mask, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) spin_lock_irqsave(&master->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) __fsi_reg_mask_set(master->base + reg, mask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) spin_unlock_irqrestore(&master->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * basic function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int fsi_version(struct fsi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return master->core->ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return fsi->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int fsi_is_clk_master(struct fsi_priv *fsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return fsi->clk_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int fsi_is_port_a(struct fsi_priv *fsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return fsi->master->base == fsi->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int fsi_is_spdif(struct fsi_priv *fsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return fsi->spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int fsi_is_enable_stream(struct fsi_priv *fsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return fsi->enable_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int fsi_is_play(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return asoc_rtd_to_cpu(rtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (dai->id == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return &master->fsia;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return &master->fsib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return fsi_get_priv_frm_dai(fsi_get_dai(substream));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int is_play = fsi_stream_is_play(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int is_porta = fsi_is_port_a(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u32 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (is_porta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) shift = is_play ? AO_SHIFT : AI_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) shift = is_play ? BO_SHIFT : BI_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return frames * fsi->chan_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return samples / fsi->chan_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int fsi_get_current_fifo_samples(struct fsi_priv *fsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct fsi_stream *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int is_play = fsi_stream_is_play(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) status = is_play ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) fsi_reg_read(fsi, DOFF_ST) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) fsi_reg_read(fsi, DIFF_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) frames = 0x1ff & (status >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return fsi_frame2sample(fsi, frames);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static void fsi_count_fifo_err(struct fsi_priv *fsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u32 istatus = fsi_reg_read(fsi, DIFF_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (ostatus & ERR_OVER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) fsi->playback.oerr_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (ostatus & ERR_UNDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) fsi->playback.uerr_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (istatus & ERR_OVER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) fsi->capture.oerr_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (istatus & ERR_UNDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) fsi->capture.uerr_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) fsi_reg_write(fsi, DOFF_ST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) fsi_reg_write(fsi, DIFF_ST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * fsi_stream_xx() function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return fsi_is_play(substream) ? &fsi->playback : &fsi->capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static int fsi_stream_is_working(struct fsi_priv *fsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct fsi_stream *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct fsi_master *master = fsi_get_master(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) spin_lock_irqsave(&master->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ret = !!(io->substream && io->substream->runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) spin_unlock_irqrestore(&master->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return io->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static void fsi_stream_init(struct fsi_priv *fsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct fsi_stream *io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct fsi_master *master = fsi_get_master(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) spin_lock_irqsave(&master->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) io->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) io->buff_sample_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) io->period_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) io->sample_width = samples_to_bytes(runtime, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) io->bus_option = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) io->oerr_num = -1; /* ignore 1st err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) io->uerr_num = -1; /* ignore 1st err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) fsi_stream_handler_call(io, init, fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) spin_unlock_irqrestore(&master->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct snd_soc_dai *dai = fsi_get_dai(io->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct fsi_master *master = fsi_get_master(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) spin_lock_irqsave(&master->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (io->oerr_num > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (io->uerr_num > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) fsi_stream_handler_call(io, quit, fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) io->substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) io->buff_sample_capa = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) io->buff_sample_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) io->period_samples = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) io->period_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) io->sample_width = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) io->bus_option = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) io->oerr_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) io->uerr_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) spin_unlock_irqrestore(&master->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int fsi_stream_transfer(struct fsi_stream *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct fsi_priv *fsi = fsi_stream_to_priv(io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (!fsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return fsi_stream_handler_call(io, transfer, fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define fsi_stream_start(fsi, io)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) fsi_stream_handler_call(io, start_stop, fsi, io, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define fsi_stream_stop(fsi, io)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) fsi_stream_handler_call(io, start_stop, fsi, io, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct fsi_stream *io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int ret1, ret2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) io = &fsi->playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) io = &fsi->capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (ret1 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return ret1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (ret2 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return ret2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int fsi_stream_remove(struct fsi_priv *fsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct fsi_stream *io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int ret1, ret2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) io = &fsi->playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret1 = fsi_stream_handler_call(io, remove, fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) io = &fsi->capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ret2 = fsi_stream_handler_call(io, remove, fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (ret1 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return ret1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (ret2 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return ret2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * format/bus/dma setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u32 bus, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct fsi_master *master = fsi_get_master(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int is_play = fsi_stream_is_play(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u32 fmt = fsi->fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (fsi_version(master) >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u32 dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * FSI2 needs DMA/Bus setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) switch (bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) case PACKAGE_24BITBUS_FRONT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) fmt |= CR_BWS_24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dma |= VDMD_FRONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) dev_dbg(dev, "24bit bus / package in front\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) case PACKAGE_16BITBUS_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) fmt |= CR_BWS_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) dma |= VDMD_STREAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) dev_dbg(dev, "16bit bus / stream mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) case PACKAGE_24BITBUS_BACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) fmt |= CR_BWS_24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dma |= VDMD_BACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) dev_dbg(dev, "24bit bus / package in back\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (is_play)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) fsi_reg_write(fsi, OUT_DMAC, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) fsi_reg_write(fsi, IN_DMAC, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (is_play)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) fsi_reg_write(fsi, DO_FMT, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) fsi_reg_write(fsi, DI_FMT, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * irq function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct fsi_master *master = fsi_get_master(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) fsi_core_mask_set(master, imsk, data, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) fsi_core_mask_set(master, iemsk, data, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct fsi_master *master = fsi_get_master(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) fsi_core_mask_set(master, imsk, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) fsi_core_mask_set(master, iemsk, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static u32 fsi_irq_get_status(struct fsi_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return fsi_core_read(master, int_st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static void fsi_irq_clear_status(struct fsi_priv *fsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct fsi_master *master = fsi_get_master(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* clear interrupt factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) fsi_core_mask_set(master, int_st, data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * SPDIF master clock function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * These functions are used later FSI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct fsi_master *master = fsi_get_master(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) mask = BP | SE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) val = enable ? mask : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) fsi_is_port_a(fsi) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) fsi_core_mask_set(master, a_mclk, mask, val) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) fsi_core_mask_set(master, b_mclk, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * clock function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static int fsi_clk_init(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct fsi_priv *fsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int xck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int ick,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) int (*set_rate)(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct fsi_priv *fsi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct fsi_clk *clock = &fsi->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) int is_porta = fsi_is_port_a(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) clock->xck = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) clock->ick = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) clock->div = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) clock->rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) clock->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) clock->set_rate = set_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) clock->own = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (IS_ERR(clock->own))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* external clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (xck) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (IS_ERR(clock->xck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) dev_err(dev, "can't get xck clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (clock->xck == clock->own) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) dev_err(dev, "cpu doesn't support xck clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* FSIACLK/FSIBCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (ick) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (IS_ERR(clock->ick)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dev_err(dev, "can't get ick clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (clock->ick == clock->own) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dev_err(dev, "cpu doesn't support ick clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* FSI-DIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (IS_ERR(clock->div)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) dev_err(dev, "can't get div clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (clock->div == clock->own) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev_err(dev, "cpu doesn't support div clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) fsi->clock.rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static int fsi_clk_is_valid(struct fsi_priv *fsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return fsi->clock.set_rate &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) fsi->clock.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static int fsi_clk_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct fsi_priv *fsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct fsi_clk *clock = &fsi->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (!fsi_clk_is_valid(fsi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (0 == clock->count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ret = clock->set_rate(dev, fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) fsi_clk_invalid(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ret = clk_enable(clock->xck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ret = clk_enable(clock->ick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) goto disable_xck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ret = clk_enable(clock->div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) goto disable_ick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) clock->count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) disable_ick:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) clk_disable(clock->ick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) disable_xck:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) clk_disable(clock->xck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int fsi_clk_disable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct fsi_priv *fsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct fsi_clk *clock = &fsi->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (!fsi_clk_is_valid(fsi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (1 == clock->count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) clk_disable(clock->xck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) clk_disable(clock->ick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) clk_disable(clock->div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int fsi_clk_set_ackbpf(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct fsi_priv *fsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) int ackmd, int bpfmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* check ackmd/bpfmd relationship */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (bpfmd > ackmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* ACKMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) switch (ackmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) case 512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) data |= (0x0 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) case 256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) data |= (0x1 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) case 128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) data |= (0x2 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) data |= (0x3 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) data |= (0x4 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dev_err(dev, "unsupported ackmd (%d)\n", ackmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* BPFMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) switch (bpfmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) data |= (0x0 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) data |= (0x1 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) case 128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) data |= (0x2 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) case 256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) data |= (0x3 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) case 512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) data |= (0x4 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) data |= (0x7 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static int fsi_clk_set_rate_external(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct fsi_priv *fsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct clk *xck = fsi->clock.xck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct clk *ick = fsi->clock.ick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) unsigned long rate = fsi->clock.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) unsigned long xrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) int ackmd, bpfmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* check clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) xrate = clk_get_rate(xck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (xrate % rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) dev_err(dev, "unsupported clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) clk_set_parent(ick, xck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) clk_set_rate(ick, xrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) bpfmd = fsi->chan_num * 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ackmd = xrate / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) dev_err(dev, "%s failed", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static int fsi_clk_set_rate_cpg(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct fsi_priv *fsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct clk *ick = fsi->clock.ick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct clk *div = fsi->clock.div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) unsigned long rate = fsi->clock.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) unsigned long target = 0; /* 12288000 or 11289600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) unsigned long actual, cout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) unsigned long diff, min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) unsigned long best_cout, best_act;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) int adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) int ackmd, bpfmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (!(12288000 % rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) target = 12288000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (!(11289600 % rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) target = 11289600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (!target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) dev_err(dev, "unsupported rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) bpfmd = fsi->chan_num * 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ackmd = target / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) dev_err(dev, "%s failed", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * The clock flow is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * But, it needs to find best match of CPG and FSI_DIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * combination, since it is difficult to generate correct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) * frequency of audio clock from ick clock only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * Because ick is created from its parent clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * target = rate x [512/256/128/64]fs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * cout = round(target x adjustment)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * actual = cout / adjustment (by FSI-DIV) ~= target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * audio = actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) min = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) best_cout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) best_act = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) for (adj = 1; adj < 0xffff; adj++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) cout = target * adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (cout > 100000000) /* max clock = 100MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /* cout/actual audio clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) cout = clk_round_rate(ick, cout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) actual = cout / adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /* find best frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) diff = abs(actual - target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (diff < min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) min = diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) best_cout = cout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) best_act = actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) ret = clk_set_rate(ick, best_cout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) dev_err(dev, "ick clock failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ret = clk_set_rate(div, clk_round_rate(div, best_act));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) dev_err(dev, "div clock failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) dev_dbg(dev, "ick/div = %ld/%ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) clk_get_rate(ick), clk_get_rate(div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static void fsi_pointer_update(struct fsi_stream *io, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) io->buff_sample_pos += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (io->buff_sample_pos >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) io->period_samples * (io->period_pos + 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct snd_pcm_substream *substream = io->substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) io->period_pos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (io->period_pos >= runtime->periods) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) io->buff_sample_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) io->period_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) snd_pcm_period_elapsed(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * pio data transfer handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (fsi_is_enable_stream(fsi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * stream mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * fsi_pio_push_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) u32 *buf = (u32 *)_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) for (i = 0; i < samples / 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) fsi_reg_write(fsi, DODT, buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /* normal mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) u16 *buf = (u16 *)_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) for (i = 0; i < samples; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) u16 *buf = (u16 *)_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) for (i = 0; i < samples; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) u32 *buf = (u32 *)_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) for (i = 0; i < samples; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) fsi_reg_write(fsi, DODT, *(buf + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) u32 *buf = (u32 *)_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) for (i = 0; i < samples; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) *(buf + i) = fsi_reg_read(fsi, DIDT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct snd_pcm_runtime *runtime = io->substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return runtime->dma_area +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) samples_to_bytes(runtime, io->buff_sample_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) int samples)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (!fsi_stream_is_working(fsi, io))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) buf = fsi_pio_get_area(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) switch (io->sample_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) run16(fsi, buf, samples);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) run32(fsi, buf, samples);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) fsi_pointer_update(io, samples);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) int sample_residues; /* samples in FSI fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) int sample_space; /* ALSA free samples space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) int samples;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) sample_residues = fsi_get_current_fifo_samples(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) sample_space = io->buff_sample_capa - io->buff_sample_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) samples = min(sample_residues, sample_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return fsi_pio_transfer(fsi, io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) fsi_pio_pop16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) fsi_pio_pop32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) samples);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) int sample_residues; /* ALSA residue samples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) int sample_space; /* FSI fifo free samples space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) int samples;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) sample_residues = io->buff_sample_capa - io->buff_sample_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) sample_space = io->fifo_sample_capa -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) fsi_get_current_fifo_samples(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) samples = min(sample_residues, sample_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return fsi_pio_transfer(fsi, io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) fsi_pio_push16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) fsi_pio_push32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) samples);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct fsi_master *master = fsi_get_master(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) fsi_irq_enable(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) fsi_irq_disable(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (fsi_is_clk_master(fsi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * we can use 16bit stream mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * when "playback" and "16bit data"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) * and platform allows "stream mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) * see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) * fsi_pio_push16()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (fsi_is_enable_stream(fsi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * always 24bit bus, package back when "capture"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static struct fsi_stream_handler fsi_pio_push_handler = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .init = fsi_pio_push_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .transfer = fsi_pio_push,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .start_stop = fsi_pio_start_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) static struct fsi_stream_handler fsi_pio_pop_handler = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .init = fsi_pio_pop_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .transfer = fsi_pio_pop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .start_stop = fsi_pio_start_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) static irqreturn_t fsi_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct fsi_master *master = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) u32 int_st = fsi_irq_get_status(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /* clear irq status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) fsi_master_mask_set(master, SOFT_RST, IR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) fsi_master_mask_set(master, SOFT_RST, IR, IR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (int_st & AB_IO(1, AO_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) fsi_stream_transfer(&master->fsia.playback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (int_st & AB_IO(1, BO_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) fsi_stream_transfer(&master->fsib.playback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (int_st & AB_IO(1, AI_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) fsi_stream_transfer(&master->fsia.capture);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (int_st & AB_IO(1, BI_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) fsi_stream_transfer(&master->fsib.capture);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) fsi_count_fifo_err(&master->fsia);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) fsi_count_fifo_err(&master->fsib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) fsi_irq_clear_status(&master->fsia);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) fsi_irq_clear_status(&master->fsib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) * dma data transfer handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) * 24bit data : 24bit bus / package in back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * 16bit data : 16bit bus / stream mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static void fsi_dma_complete(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) struct fsi_stream *io = (struct fsi_stream *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) struct fsi_priv *fsi = fsi_stream_to_priv(io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) fsi_pointer_update(io, io->period_samples);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) fsi_count_fifo_err(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) struct snd_soc_dai *dai = fsi_get_dai(io->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct snd_pcm_substream *substream = io->substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) int is_play = fsi_stream_is_play(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) enum dma_transfer_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) int ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (is_play)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) dir = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) dir = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) desc = dmaengine_prep_dma_cyclic(io->chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) substream->runtime->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) snd_pcm_lib_buffer_bytes(substream),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) snd_pcm_lib_period_bytes(substream),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) dev_err(dai->dev, "dmaengine_prep_dma_cyclic() fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) goto fsi_dma_transfer_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) desc->callback = fsi_dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) desc->callback_param = io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (dmaengine_submit(desc) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) dev_err(dai->dev, "tx_submit() fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) goto fsi_dma_transfer_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) dma_async_issue_pending(io->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) * FIXME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * In DMAEngine case, codec and FSI cannot be started simultaneously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * since FSI is using the scheduler work queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * Therefore, in capture case, probably FSI FIFO will have got
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * overflow error in this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * in that case, DMA cannot start transfer until error was cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (!is_play) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) fsi_reg_write(fsi, DIFF_ST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) fsi_dma_transfer_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) int start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct fsi_master *master = fsi_get_master(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) u32 enable = start ? DMA_ON : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) dmaengine_terminate_all(io->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (fsi_is_clk_master(fsi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) int is_play = fsi_stream_is_play(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) #ifdef CONFIG_SUPERH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) dma_cap_set(DMA_SLAVE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) io->chan = dma_request_channel(mask, shdma_chan_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) (void *)io->dma_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) io->chan = dma_request_slave_channel(dev, is_play ? "tx" : "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (io->chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) struct dma_slave_config cfg = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (is_play) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) cfg.dst_addr = fsi->phys + REG_DODT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) cfg.direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) cfg.src_addr = fsi->phys + REG_DIDT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) cfg.direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) ret = dmaengine_slave_config(io->chan, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) dma_release_channel(io->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) io->chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (!io->chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) /* switch to PIO handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (is_play)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) fsi->playback.handler = &fsi_pio_push_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) fsi->capture.handler = &fsi_pio_pop_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) dev_info(dev, "switch handler (dma => pio)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) /* probe again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) return fsi_stream_probe(fsi, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) fsi_stream_stop(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (io->chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) dma_release_channel(io->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) io->chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static struct fsi_stream_handler fsi_dma_push_handler = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .init = fsi_dma_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .probe = fsi_dma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .transfer = fsi_dma_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .remove = fsi_dma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .start_stop = fsi_dma_push_start_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * dai ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) static void fsi_fifo_init(struct fsi_priv *fsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) struct fsi_stream *io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) struct fsi_master *master = fsi_get_master(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) int is_play = fsi_stream_is_play(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) u32 shift, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) int frame_capa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /* get on-chip RAM capacity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) shift = fsi_master_read(master, FIFO_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) shift >>= fsi_get_port_shift(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) shift &= FIFO_SZ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) frame_capa = 256 << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) dev_dbg(dev, "fifo = %d words\n", frame_capa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) * The maximum number of sample data varies depending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * on the number of channels selected for the format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) * FIFOs are used in 4-channel units in 3-channel mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) * and in 8-channel units in 5- to 7-channel mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) * meaning that more FIFOs than the required size of DPRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) * are used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * ex) if 256 words of DP-RAM is connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) * 1 channel: 256 (256 x 1 = 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) * 2 channels: 128 (128 x 2 = 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) * 3 channels: 64 ( 64 x 3 = 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) * 4 channels: 64 ( 64 x 4 = 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) * 5 channels: 32 ( 32 x 5 = 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) * 6 channels: 32 ( 32 x 6 = 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) * 7 channels: 32 ( 32 x 7 = 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) * 8 channels: 32 ( 32 x 8 = 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) for (i = 1; i < fsi->chan_num; i <<= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) frame_capa >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) dev_dbg(dev, "%d channel %d store\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) fsi->chan_num, frame_capa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) * set interrupt generation factor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) * clear FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (is_play) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) static int fsi_hw_startup(struct fsi_priv *fsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) struct fsi_stream *io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) /* clock setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) if (fsi_is_clk_master(fsi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) data = DIMD | DOMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /* clock inversion (CKG2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) if (fsi->bit_clk_inv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) data |= (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (fsi->lr_clk_inv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) data |= (1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) if (fsi_is_clk_master(fsi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) data <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) fsi_reg_write(fsi, CKG2, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* spdif ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (fsi_is_spdif(fsi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) fsi_spdif_clk_ctrl(fsi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) * get bus settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) switch (io->sample_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) data = BUSOP_GET(16, io->bus_option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) data = BUSOP_GET(24, io->bus_option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) fsi_format_bus_setup(fsi, io, data, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /* irq clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) fsi_irq_disable(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) fsi_irq_clear_status(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) /* fifo init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) fsi_fifo_init(fsi, io, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) /* start master clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if (fsi_is_clk_master(fsi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) return fsi_clk_enable(dev, fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) static int fsi_hw_shutdown(struct fsi_priv *fsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) /* stop master clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) if (fsi_is_clk_master(fsi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) return fsi_clk_disable(dev, fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) static int fsi_dai_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) struct fsi_priv *fsi = fsi_get_priv(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) fsi_clk_invalid(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) struct fsi_priv *fsi = fsi_get_priv(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) fsi_clk_invalid(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) struct fsi_priv *fsi = fsi_get_priv(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) struct fsi_stream *io = fsi_stream_get(fsi, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) fsi_stream_init(fsi, io, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) ret = fsi_hw_startup(fsi, io, dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) ret = fsi_stream_start(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) ret = fsi_stream_transfer(io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) ret = fsi_hw_shutdown(fsi, dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) fsi_stream_stop(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) fsi_stream_quit(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) fsi->fmt = CR_I2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) fsi->chan_num = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) fsi->fmt = CR_PCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) fsi->chan_num = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) struct fsi_master *master = fsi_get_master(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (fsi_version(master) < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) fsi->chan_num = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) /* set clock master audio interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) fsi->clk_master = 1; /* cpu is master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) /* set clock inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) fsi->bit_clk_inv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) fsi->lr_clk_inv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) fsi->bit_clk_inv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) fsi->lr_clk_inv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) fsi->bit_clk_inv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) fsi->lr_clk_inv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) fsi->bit_clk_inv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) fsi->lr_clk_inv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (fsi_is_clk_master(fsi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if (fsi->clk_cpg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) fsi_clk_init(dai->dev, fsi, 0, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) fsi_clk_set_rate_cpg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) fsi_clk_init(dai->dev, fsi, 1, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) fsi_clk_set_rate_external);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) /* set format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if (fsi_is_spdif(fsi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) ret = fsi_set_fmt_spdif(fsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) struct fsi_priv *fsi = fsi_get_priv(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) if (fsi_is_clk_master(fsi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) fsi_clk_valid(fsi, params_rate(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) static const struct snd_soc_dai_ops fsi_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .startup = fsi_dai_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .shutdown = fsi_dai_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .trigger = fsi_dai_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .set_fmt = fsi_dai_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .hw_params = fsi_dai_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) * pcm ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static const struct snd_pcm_hardware fsi_pcm_hardware = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .info = SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) SNDRV_PCM_INFO_MMAP_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .buffer_bytes_max = 64 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .period_bytes_min = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .period_bytes_max = 8192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .periods_max = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .fifo_size = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) static int fsi_pcm_open(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) ret = snd_pcm_hw_constraint_integer(runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) SNDRV_PCM_HW_PARAM_PERIODS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) static snd_pcm_uframes_t fsi_pointer(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) struct fsi_priv *fsi = fsi_get_priv(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) struct fsi_stream *io = fsi_stream_get(fsi, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) return fsi_sample2frame(fsi, io->buff_sample_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) * snd_soc_component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) #define PREALLOC_BUFFER (32 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) #define PREALLOC_BUFFER_MAX (32 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) static int fsi_pcm_new(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) struct snd_soc_pcm_runtime *rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) snd_pcm_set_managed_buffer_all(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) rtd->pcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) rtd->card->snd_card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) * alsa struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) static struct snd_soc_dai_driver fsi_soc_dai[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .name = "fsia-dai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .rates = FSI_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .formats = FSI_FMTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .rates = FSI_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .formats = FSI_FMTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .ops = &fsi_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .name = "fsib-dai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .rates = FSI_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .formats = FSI_FMTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .rates = FSI_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .formats = FSI_FMTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .ops = &fsi_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) static const struct snd_soc_component_driver fsi_soc_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .name = "fsi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .open = fsi_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .pointer = fsi_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .pcm_construct = fsi_pcm_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) * platform function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) static void fsi_of_parse(char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) struct sh_fsi_port_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) char prop[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) } of_parse_property[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) { "spdif-connection", SH_FSI_FMT_SPDIF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) { "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) { "use-internal-clock", SH_FSI_CLK_CPG },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) sprintf(prop, "%s,%s", name, of_parse_property[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) if (of_get_property(np, prop, NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) flags |= of_parse_property[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) info->flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) dev_dbg(dev, "%s flags : %lx\n", name, info->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) static void fsi_port_info_init(struct fsi_priv *fsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) struct sh_fsi_port_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) if (info->flags & SH_FSI_FMT_SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) fsi->spdif = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (info->flags & SH_FSI_CLK_CPG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) fsi->clk_cpg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (info->flags & SH_FSI_ENABLE_STREAM_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) fsi->enable_stream = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) static void fsi_handler_init(struct fsi_priv *fsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) struct sh_fsi_port_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) fsi->playback.priv = fsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) fsi->capture.priv = fsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) if (info->tx_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) fsi->playback.dma_id = info->tx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) fsi->playback.handler = &fsi_dma_push_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) static const struct fsi_core fsi1_core = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .ver = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) /* Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .int_st = INT_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .iemsk = IEMSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .imsk = IMSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) static const struct fsi_core fsi2_core = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .ver = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) /* Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .int_st = CPU_INT_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .iemsk = CPU_IEMSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .imsk = CPU_IMSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .a_mclk = A_MST_CTLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .b_mclk = B_MST_CTLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) static const struct of_device_id fsi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) { .compatible = "renesas,sh_fsi", .data = &fsi1_core},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) { .compatible = "renesas,sh_fsi2", .data = &fsi2_core},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) MODULE_DEVICE_TABLE(of, fsi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) static const struct platform_device_id fsi_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) { "sh_fsi", (kernel_ulong_t)&fsi1_core },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) MODULE_DEVICE_TABLE(platform, fsi_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) static int fsi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) struct fsi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) struct sh_fsi_platform_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) const struct fsi_core *core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) struct fsi_priv *fsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) memset(&info, 0, sizeof(info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) core = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) core = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) fsi_of_parse("fsia", np, &info.port_a, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) fsi_of_parse("fsib", np, &info.port_b, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) const struct platform_device_id *id_entry = pdev->id_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) if (id_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) core = (struct fsi_core *)id_entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) if (pdev->dev.platform_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) memcpy(&info, pdev->dev.platform_data, sizeof(info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (!core) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) dev_err(&pdev->dev, "unknown fsi device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) if (!res || (int)irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) master->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (!master->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) /* master setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) master->core = core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) spin_lock_init(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) /* FSI A setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) fsi = &master->fsia;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) fsi->base = master->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) fsi->phys = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) fsi->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) fsi_port_info_init(fsi, &info.port_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) fsi_handler_init(fsi, &info.port_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) ret = fsi_stream_probe(fsi, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) dev_err(&pdev->dev, "FSIA stream probe failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) /* FSI B setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) fsi = &master->fsib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) fsi->base = master->base + 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) fsi->phys = res->start + 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) fsi->master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) fsi_port_info_init(fsi, &info.port_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) fsi_handler_init(fsi, &info.port_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) ret = fsi_stream_probe(fsi, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) dev_err(&pdev->dev, "FSIB stream probe failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) goto exit_fsia;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) dev_set_drvdata(&pdev->dev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) dev_name(&pdev->dev), master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) dev_err(&pdev->dev, "irq request err\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) goto exit_fsib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) ret = devm_snd_soc_register_component(&pdev->dev, &fsi_soc_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) dev_err(&pdev->dev, "cannot snd component register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) goto exit_fsib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) exit_fsib:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) fsi_stream_remove(&master->fsib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) exit_fsia:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) fsi_stream_remove(&master->fsia);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) static int fsi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) struct fsi_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) master = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) fsi_stream_remove(&master->fsia);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) fsi_stream_remove(&master->fsib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) static void __fsi_suspend(struct fsi_priv *fsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) struct fsi_stream *io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) if (!fsi_stream_is_working(fsi, io))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) fsi_stream_stop(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) fsi_hw_shutdown(fsi, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) static void __fsi_resume(struct fsi_priv *fsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) struct fsi_stream *io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) if (!fsi_stream_is_working(fsi, io))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) fsi_hw_startup(fsi, io, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) fsi_stream_start(fsi, io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) static int fsi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) struct fsi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) struct fsi_priv *fsia = &master->fsia;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) struct fsi_priv *fsib = &master->fsib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) __fsi_suspend(fsia, &fsia->playback, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) __fsi_suspend(fsia, &fsia->capture, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) __fsi_suspend(fsib, &fsib->playback, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) __fsi_suspend(fsib, &fsib->capture, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) static int fsi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) struct fsi_master *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) struct fsi_priv *fsia = &master->fsia;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) struct fsi_priv *fsib = &master->fsib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) __fsi_resume(fsia, &fsia->playback, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) __fsi_resume(fsia, &fsia->capture, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) __fsi_resume(fsib, &fsib->playback, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) __fsi_resume(fsib, &fsib->capture, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) static const struct dev_pm_ops fsi_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .suspend = fsi_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .resume = fsi_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) static struct platform_driver fsi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .name = "fsi-pcm-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .pm = &fsi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .of_match_table = fsi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .probe = fsi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .remove = fsi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .id_table = fsi_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) module_platform_driver(fsi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) MODULE_ALIAS("platform:fsi-pcm-audio");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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