Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // SH7760 ("camelot") DMABRG audio DMA unit support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (C) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // The SH7760 DMABRG provides 4 dma channels (2x rec, 2x play), which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) // trigger an interrupt when one half of the programmed transfer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) // has been xmitted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) // FIXME: little-endian only for now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/dmabrg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* registers and bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define BRGATXSAR	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define BRGARXDAR	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define BRGATXTCR	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define BRGARXTCR	0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define BRGACR		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define BRGATXTCNT	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define BRGARXTCNT	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ACR_RAR		(1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define ACR_RDS		(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ACR_RDE		(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define ACR_TAR		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define ACR_TDS		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define ACR_TDE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* receiver/transmitter data alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ACR_RAM_NONE	(0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define ACR_RAM_4BYTE	(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define ACR_RAM_2WORD	(2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define ACR_TAM_NONE	(0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define ACR_TAM_4BYTE	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define ACR_TAM_2WORD	(2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) struct camelot_pcm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	unsigned long mmio;  /* DMABRG audio channel control reg MMIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	unsigned int txid;    /* ID of first DMABRG IRQ for this unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct snd_pcm_substream *tx_ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	unsigned long tx_period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	unsigned int  tx_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct snd_pcm_substream *rx_ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	unsigned long rx_period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	unsigned int  rx_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) } cam_pcm_data[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.mmio	=	0xFE3C0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		.txid	=	DMABRGIRQ_A0TXF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.mmio	=	0xFE3C0060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.txid	=	DMABRGIRQ_A1TXF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define BRGREG(x)	(*(unsigned long *)(cam->mmio + (x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * set a minimum of 16kb per period, to avoid interrupt-"storm" and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * resulting skipping. In general, the bigger the minimum size, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * better for overall system performance. (The SH7760 is a puny CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * with a slow SDRAM interface and poor internal bus bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * *especially* when the LCDC is active).  The minimum for the DMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * is 8 bytes; 16kbytes are enough to get skip-free playback of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * 44kHz/16bit/stereo MP3 on a lightly loaded system, and maintain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * reasonable responsiveness in MPlayer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define DMABRG_PERIOD_MIN		16 * 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define DMABRG_PERIOD_MAX		0x03fffffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define DMABRG_PREALLOC_BUFFER		32 * 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define DMABRG_PREALLOC_BUFFER_MAX	32 * 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static const struct snd_pcm_hardware camelot_pcm_hardware = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.info = (SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		SNDRV_PCM_INFO_BATCH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.buffer_bytes_max =	DMABRG_PERIOD_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.period_bytes_min =	DMABRG_PERIOD_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.period_bytes_max =	DMABRG_PERIOD_MAX / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.periods_min =		2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.periods_max =		2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.fifo_size =		128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void camelot_txdma(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct camelot_pcm *cam = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	cam->tx_period ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	snd_pcm_period_elapsed(cam->tx_ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void camelot_rxdma(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct camelot_pcm *cam = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	cam->rx_period ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	snd_pcm_period_elapsed(cam->rx_ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int camelot_pcm_open(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			    struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct camelot_pcm *cam = &cam_pcm_data[asoc_rtd_to_cpu(rtd, 0)->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	int ret, dmairq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	snd_soc_set_runtime_hwparams(substream, &camelot_pcm_hardware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/* DMABRG buffer half/full events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	dmairq = (recv) ? cam->txid + 2 : cam->txid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (recv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		cam->rx_ss = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		ret = dmabrg_request_irq(dmairq, camelot_rxdma, cam);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		if (unlikely(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			pr_debug("audio unit %d irqs already taken!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			     asoc_rtd_to_cpu(rtd, 0)->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		(void)dmabrg_request_irq(dmairq + 1,camelot_rxdma, cam);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		cam->tx_ss = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		ret = dmabrg_request_irq(dmairq, camelot_txdma, cam);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		if (unlikely(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			pr_debug("audio unit %d irqs already taken!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			     asoc_rtd_to_cpu(rtd, 0)->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		(void)dmabrg_request_irq(dmairq + 1, camelot_txdma, cam);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int camelot_pcm_close(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			     struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	struct camelot_pcm *cam = &cam_pcm_data[asoc_rtd_to_cpu(rtd, 0)->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	int dmairq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	dmairq = (recv) ? cam->txid + 2 : cam->txid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (recv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		cam->rx_ss = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		cam->tx_ss = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	dmabrg_free_irq(dmairq + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	dmabrg_free_irq(dmairq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int camelot_hw_params(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			     struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			     struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct camelot_pcm *cam = &cam_pcm_data[asoc_rtd_to_cpu(rtd, 0)->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (recv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		cam->rx_period_size = params_period_bytes(hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		cam->rx_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		cam->tx_period_size = params_period_bytes(hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		cam->tx_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int camelot_prepare(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			   struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct camelot_pcm *cam = &cam_pcm_data[asoc_rtd_to_cpu(rtd, 0)->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	pr_debug("PCM data: addr 0x%08lx len %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		 (u32)runtime->dma_addr, runtime->dma_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		BRGREG(BRGATXSAR) = (unsigned long)runtime->dma_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		BRGREG(BRGATXTCR) = runtime->dma_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		BRGREG(BRGARXDAR) = (unsigned long)runtime->dma_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		BRGREG(BRGARXTCR) = runtime->dma_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static inline void dmabrg_play_dma_start(struct camelot_pcm *cam)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	/* start DMABRG engine: XFER start, auto-addr-reload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	BRGREG(BRGACR) = acr | ACR_TDE | ACR_TAR | ACR_TAM_2WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static inline void dmabrg_play_dma_stop(struct camelot_pcm *cam)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* forcibly terminate data transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	BRGREG(BRGACR) = acr | ACR_TDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static inline void dmabrg_rec_dma_start(struct camelot_pcm *cam)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/* start DMABRG engine: recv start, auto-reload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	BRGREG(BRGACR) = acr | ACR_RDE | ACR_RAR | ACR_RAM_2WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static inline void dmabrg_rec_dma_stop(struct camelot_pcm *cam)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	unsigned long acr = BRGREG(BRGACR) & ~(ACR_TDS | ACR_RDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	/* forcibly terminate data receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	BRGREG(BRGACR) = acr | ACR_RDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int camelot_trigger(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			   struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct camelot_pcm *cam = &cam_pcm_data[asoc_rtd_to_cpu(rtd, 0)->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		if (recv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			dmabrg_rec_dma_start(cam);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			dmabrg_play_dma_start(cam);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		if (recv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			dmabrg_rec_dma_stop(cam);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			dmabrg_play_dma_stop(cam);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static snd_pcm_uframes_t camelot_pos(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 				     struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	struct camelot_pcm *cam = &cam_pcm_data[asoc_rtd_to_cpu(rtd, 0)->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	int recv = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	unsigned long pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	/* cannot use the DMABRG pointer register: under load, by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	 * time ALSA comes around to read the register, it is already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	 * far ahead (or worse, already done with the fragment) of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	 * position at the time the IRQ was triggered, which results in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	 * fast-playback sound in my test application (ScummVM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (recv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		pos = cam->rx_period ? cam->rx_period_size : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		pos = cam->tx_period ? cam->tx_period_size : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	return bytes_to_frames(runtime, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int camelot_pcm_new(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			   struct snd_soc_pcm_runtime *rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	struct snd_pcm *pcm = rtd->pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	/* dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	 * in MMAP mode (i.e. aplay -M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	snd_pcm_set_managed_buffer_all(pcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		SNDRV_DMA_TYPE_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		DMABRG_PREALLOC_BUFFER,	DMABRG_PREALLOC_BUFFER_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const struct snd_soc_component_driver sh7760_soc_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.open		= camelot_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.close		= camelot_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.hw_params	= camelot_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.prepare	= camelot_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	.trigger	= camelot_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.pointer	= camelot_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	.pcm_construct	= camelot_pcm_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int sh7760_soc_platform_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	return devm_snd_soc_register_component(&pdev->dev, &sh7760_soc_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 					       NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static struct platform_driver sh7760_pcm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			.name = "sh7760-pcm-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.probe = sh7760_soc_platform_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) module_platform_driver(sh7760_pcm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MODULE_DESCRIPTION("SH7760 Audio DMA (DMABRG) driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MODULE_AUTHOR("Manuel Lauss <mano@roarinelk.homelinux.net>");