^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // ALSA SoC Audio Layer - Samsung S/PDIF Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2010 Samsung Electronics Co. Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // http://www.samsung.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_data/asoc-s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "spdif.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLKCON 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CON 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BSTAS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CSTAS 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DATA_OUTBUF 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DCNT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BSTAS_S 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DCNT_S 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLKCTL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLKCTL_MCLK_EXT (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLKCTL_PWR_ON (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CON_MASK 0x3ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CON_FIFO_TH_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CON_FIFO_TH_MASK (0x7 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CON_USERDATA_23RDBIT (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CON_SW_RESET (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CON_MCLKDIV_MASK (0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CON_MCLKDIV_256FS (0x0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CON_MCLKDIV_384FS (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CON_MCLKDIV_512FS (0x2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CON_PCM_MASK (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CON_PCM_16BIT (0x0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CON_PCM_20BIT (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CON_PCM_24BIT (0x2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CON_PCM_DATA (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CSTAS_MASK 0x3fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CSTAS_SAMP_FREQ_MASK (0xF << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CSTAS_SAMP_FREQ_44 (0x0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CSTAS_SAMP_FREQ_48 (0x2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CSTAS_SAMP_FREQ_32 (0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CSTAS_SAMP_FREQ_96 (0xA << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CSTAS_CATEGORY_MASK (0xFF << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CSTAS_CATEGORY_CODE_CDP (0x01 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CSTAS_NO_COPYRIGHT (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * struct samsung_spdif_info - Samsung S/PDIF Controller information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @lock: Spin lock for S/PDIF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @dev: The parent device passed to use from the probe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @regs: The pointer to the device register block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @clk_rate: Current clock rate for calcurate ratio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @pclk: The peri-clock pointer for spdif master operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @sclk: The source clock pointer for making sync signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @saved_clkcon: Backup clkcon reg. in suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @saved_con: Backup con reg. in suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @saved_cstas: Backup cstas reg. in suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @dma_playback: DMA information for playback channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct samsung_spdif_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct clk *sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 saved_clkcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 saved_con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 saved_cstas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct snd_dmaengine_dai_dma_data *dma_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct snd_dmaengine_dai_dma_data spdif_stereo_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static struct samsung_spdif_info spdif_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static inline struct samsung_spdif_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *component_to_info(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static inline struct samsung_spdif_info *to_info(struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void spdif_snd_txctrl(struct samsung_spdif_info *spdif, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void __iomem *regs = spdif->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 clkcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dev_dbg(spdif->dev, "Entered %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clkcon = readl(regs + CLKCON) & CLKCTL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) writel(clkcon | CLKCTL_PWR_ON, regs + CLKCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel(clkcon & ~CLKCTL_PWR_ON, regs + CLKCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int spdif_set_sysclk(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int clk_id, unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct samsung_spdif_info *spdif = to_info(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 clkcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dev_dbg(spdif->dev, "Entered %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clkcon = readl(spdif->regs + CLKCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (clk_id == SND_SOC_SPDIF_INT_MCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) clkcon &= ~CLKCTL_MCLK_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) clkcon |= CLKCTL_MCLK_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) writel(clkcon, spdif->regs + CLKCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) spdif->clk_rate = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int spdif_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct samsung_spdif_info *spdif = to_info(asoc_rtd_to_cpu(rtd, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dev_dbg(spdif->dev, "Entered %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) spin_lock_irqsave(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) spdif_snd_txctrl(spdif, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) spin_lock_irqsave(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) spdif_snd_txctrl(spdif, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int spdif_sysclk_ratios[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 512, 384, 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int spdif_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct snd_soc_dai *socdai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct samsung_spdif_info *spdif = to_info(asoc_rtd_to_cpu(rtd, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void __iomem *regs = spdif->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct snd_dmaengine_dai_dma_data *dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 con, clkcon, cstas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int i, ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dev_dbg(spdif->dev, "Entered %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dma_data = spdif->dma_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) dev_err(spdif->dev, "Capture is not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) snd_soc_dai_set_dma_data(asoc_rtd_to_cpu(rtd, 0), substream, dma_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) spin_lock_irqsave(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) con = readl(regs + CON) & CON_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) cstas = readl(regs + CSTAS) & CSTAS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) clkcon = readl(regs + CLKCON) & CLKCTL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) con &= ~CON_FIFO_TH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) con |= (0x7 << CON_FIFO_TH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) con |= CON_USERDATA_23RDBIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) con |= CON_PCM_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) con &= ~CON_PCM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) switch (params_width(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) con |= CON_PCM_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dev_err(spdif->dev, "Unsupported data size.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ratio = spdif->clk_rate / params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) for (i = 0; i < ARRAY_SIZE(spdif_sysclk_ratios); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ratio == spdif_sysclk_ratios[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (i == ARRAY_SIZE(spdif_sysclk_ratios)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_err(spdif->dev, "Invalid clock ratio %ld/%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) spdif->clk_rate, params_rate(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) con &= ~CON_MCLKDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) switch (ratio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case 256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) con |= CON_MCLKDIV_256FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case 384:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) con |= CON_MCLKDIV_384FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) case 512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) con |= CON_MCLKDIV_512FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) cstas &= ~CSTAS_SAMP_FREQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) switch (params_rate(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) cstas |= CSTAS_SAMP_FREQ_44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) cstas |= CSTAS_SAMP_FREQ_48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) cstas |= CSTAS_SAMP_FREQ_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) cstas |= CSTAS_SAMP_FREQ_96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dev_err(spdif->dev, "Invalid sampling rate %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) params_rate(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) cstas &= ~CSTAS_CATEGORY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) cstas |= CSTAS_CATEGORY_CODE_CDP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) cstas |= CSTAS_NO_COPYRIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) writel(con, regs + CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) writel(cstas, regs + CSTAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) writel(clkcon, regs + CLKCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) spin_unlock_irqrestore(&spdif->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static void spdif_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct samsung_spdif_info *spdif = to_info(asoc_rtd_to_cpu(rtd, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) void __iomem *regs = spdif->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 con, clkcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dev_dbg(spdif->dev, "Entered %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) con = readl(regs + CON) & CON_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) clkcon = readl(regs + CLKCON) & CLKCTL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) writel(con | CON_SW_RESET, regs + CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) writel(clkcon & ~CLKCTL_PWR_ON, regs + CLKCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int spdif_suspend(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct samsung_spdif_info *spdif = component_to_info(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 con = spdif->saved_con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dev_dbg(spdif->dev, "Entered %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) spdif->saved_clkcon = readl(spdif->regs + CLKCON) & CLKCTL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) spdif->saved_con = readl(spdif->regs + CON) & CON_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) spdif->saved_cstas = readl(spdif->regs + CSTAS) & CSTAS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) writel(con | CON_SW_RESET, spdif->regs + CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int spdif_resume(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct samsung_spdif_info *spdif = component_to_info(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_dbg(spdif->dev, "Entered %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) writel(spdif->saved_clkcon, spdif->regs + CLKCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) writel(spdif->saved_con, spdif->regs + CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) writel(spdif->saved_cstas, spdif->regs + CSTAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define spdif_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define spdif_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const struct snd_soc_dai_ops spdif_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .set_sysclk = spdif_set_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .trigger = spdif_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .hw_params = spdif_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .shutdown = spdif_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static struct snd_soc_dai_driver samsung_spdif_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .name = "samsung-spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .stream_name = "S/PDIF Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .rates = (SNDRV_PCM_RATE_32000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) SNDRV_PCM_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) SNDRV_PCM_RATE_96000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .formats = SNDRV_PCM_FMTBIT_S16_LE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .ops = &spdif_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct snd_soc_component_driver samsung_spdif_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .name = "samsung-spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .suspend = spdif_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .resume = spdif_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int spdif_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct s3c_audio_pdata *spdif_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct resource *mem_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct samsung_spdif_info *spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dma_filter_fn filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) spdif_pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dev_dbg(&pdev->dev, "Entered %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (!mem_res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dev_err(&pdev->dev, "Unable to get register resource.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (spdif_pdata && spdif_pdata->cfg_gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) && spdif_pdata->cfg_gpio(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev_err(&pdev->dev, "Unable to configure GPIO pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) spdif = &spdif_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) spdif->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) spin_lock_init(&spdif->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) spdif->pclk = devm_clk_get(&pdev->dev, "spdif");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (IS_ERR(spdif->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_err(&pdev->dev, "failed to get peri-clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ret = clk_prepare_enable(spdif->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) spdif->sclk = devm_clk_get(&pdev->dev, "sclk_spdif");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (IS_ERR(spdif->sclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_err(&pdev->dev, "failed to get internal source clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ret = clk_prepare_enable(spdif->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Request S/PDIF Register's memory region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (!request_mem_region(mem_res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) resource_size(mem_res), "samsung-spdif")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_err(&pdev->dev, "Unable to request register region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) spdif->regs = ioremap(mem_res->start, 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (spdif->regs == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev_err(&pdev->dev, "Cannot ioremap registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) goto err3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) spdif_stereo_out.addr_width = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) spdif_stereo_out.addr = mem_res->start + DATA_OUTBUF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) filter = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (spdif_pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) spdif_stereo_out.filter_data = spdif_pdata->dma_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) filter = spdif_pdata->dma_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) spdif->dma_playback = &spdif_stereo_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ret = samsung_asoc_dma_platform_register(&pdev->dev, filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) NULL, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_err(&pdev->dev, "failed to register DMA: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) goto err4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_set_drvdata(&pdev->dev, spdif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) &samsung_spdif_component, &samsung_spdif_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dev_err(&pdev->dev, "fail to register dai\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) goto err4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) err4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) iounmap(spdif->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) err3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) release_mem_region(mem_res->start, resource_size(mem_res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) clk_disable_unprepare(spdif->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) clk_disable_unprepare(spdif->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) err0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int spdif_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct samsung_spdif_info *spdif = &spdif_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct resource *mem_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) iounmap(spdif->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (mem_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) release_mem_region(mem_res->start, resource_size(mem_res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) clk_disable_unprepare(spdif->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) clk_disable_unprepare(spdif->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static struct platform_driver samsung_spdif_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .probe = spdif_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .remove = spdif_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .name = "samsung-spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) module_platform_driver(samsung_spdif_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) MODULE_AUTHOR("Seungwhan Youn, <sw.youn@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) MODULE_DESCRIPTION("Samsung S/PDIF Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) MODULE_ALIAS("platform:samsung-spdif");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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