^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Modifications by Christian Pellegrin <chripell@evolware.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // s3c24xx_uda134x.c - S3C24XX_UDA134X ALSA SoC Audio board driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Copyright 2007 Dension Audio Systems Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Author: Zoltan Devai
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/s3c24xx_uda134x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "regs-iis.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "s3c24xx-i2s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct s3c24xx_uda134x {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct clk *xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct mutex clk_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) int clk_users;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* #define ENFORCE_RATES 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Unfortunately the S3C24XX in master mode has a limited capacity of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) generating the clock for the codec. If you define this only rates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) that are really available will be enforced. But be careful, most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) user level application just want the usual sampling frequencies (8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 11.025, 22.050, 44.1 kHz) and anyway resampling is a costly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) operation for embedded systems. So if you aren't very lucky or your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) hardware engineer wasn't very forward-looking it's better to leave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) this undefined. If you do so an approximate value for the requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) sampling rate in the range -/+ 5% will be chosen. If this in not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) possible an error will be returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static unsigned int rates[33 * 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #ifdef ENFORCE_RATES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .count = ARRAY_SIZE(rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .list = rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int s3c24xx_uda134x_startup(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct s3c24xx_uda134x *priv = snd_soc_card_get_drvdata(rtd->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mutex_lock(&priv->clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (priv->clk_users == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) priv->xtal = clk_get(rtd->dev, "xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (IS_ERR(priv->xtal)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) dev_err(rtd->dev, "%s cannot get xtal\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ret = PTR_ERR(priv->xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) priv->pclk = clk_get(cpu_dai->dev, "iis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (IS_ERR(priv->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) dev_err(rtd->dev, "%s cannot get pclk\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) clk_put(priv->xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ret = PTR_ERR(priv->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int fs = i ? 256 : 384;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) rates[i*33] = clk_get_rate(priv->xtal) / fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) for (j = 1; j < 33; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) rates[i*33 + j] = clk_get_rate(priv->pclk) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) (j * fs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) priv->clk_users += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mutex_unlock(&priv->clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #ifdef ENFORCE_RATES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) &hw_constraints_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dev_err(rtd->dev, "%s cannot set constraints\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void s3c24xx_uda134x_shutdown(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct s3c24xx_uda134x *priv = snd_soc_card_get_drvdata(rtd->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) mutex_lock(&priv->clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) priv->clk_users -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (priv->clk_users == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) clk_put(priv->xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) priv->xtal = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clk_put(priv->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) priv->pclk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mutex_unlock(&priv->clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int s3c24xx_uda134x_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int clk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int clk_source, fs_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned long rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) long err, cerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int i, bi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) err = 999999;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) bi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) for (i = 0; i < 2*33; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) cerr = rates[i] - rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (cerr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) cerr = -cerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (cerr < err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) err = cerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) bi = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (bi / 33 == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) fs_mode = S3C2410_IISMOD_256FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) fs_mode = S3C2410_IISMOD_384FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (bi % 33 == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) clk_source = S3C24XX_CLKSRC_MPLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) clk_source = S3C24XX_CLKSRC_PCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) div = bi % 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dev_dbg(rtd->dev, "%s desired rate %lu, %d\n", __func__, rate, bi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) clk = (fs_mode == S3C2410_IISMOD_384FS ? 384 : 256) * rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev_dbg(rtd->dev, "%s will use: %s %s %d sysclk %d err %ld\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) fs_mode == S3C2410_IISMOD_384FS ? "384FS" : "256FS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) clk_source == S3C24XX_CLKSRC_MPLL ? "MPLLin" : "PCLK",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) div, clk, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if ((err * 100 / rate) > 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dev_err(rtd->dev, "effective frequency too different "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "from desired (%ld%%)\n", err * 100 / rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ret = snd_soc_dai_set_sysclk(cpu_dai, clk_source , clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) SND_SOC_CLOCK_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_MCLK, fs_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) S3C2410_IISMOD_32FS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) S3C24XX_PRESCALE(div, div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* set the codec system clock for DAC and ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ret = snd_soc_dai_set_sysclk(codec_dai, 0, clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) SND_SOC_CLOCK_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct snd_soc_ops s3c24xx_uda134x_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .startup = s3c24xx_uda134x_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .shutdown = s3c24xx_uda134x_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .hw_params = s3c24xx_uda134x_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) SND_SOC_DAILINK_DEFS(uda134x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) DAILINK_COMP_ARRAY(COMP_CPU("s3c24xx-iis")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) DAILINK_COMP_ARRAY(COMP_CODEC("uda134x-codec", "uda134x-hifi")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) DAILINK_COMP_ARRAY(COMP_PLATFORM("s3c24xx-iis")));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct snd_soc_dai_link s3c24xx_uda134x_dai_link = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .name = "UDA134X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .stream_name = "UDA134X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) SND_SOC_DAIFMT_CBS_CFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .ops = &s3c24xx_uda134x_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) SND_SOC_DAILINK_REG(uda134x),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static struct snd_soc_card snd_soc_s3c24xx_uda134x = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .name = "S3C24XX_UDA134X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .dai_link = &s3c24xx_uda134x_dai_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .num_links = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int s3c24xx_uda134x_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct snd_soc_card *card = &snd_soc_s3c24xx_uda134x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct s3c24xx_uda134x *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) mutex_init(&priv->clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) card->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) snd_soc_card_set_drvdata(card, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = devm_snd_soc_register_card(&pdev->dev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_err(&pdev->dev, "failed to register card: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct platform_driver s3c24xx_uda134x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .probe = s3c24xx_uda134x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .name = "s3c24xx_uda134x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) module_platform_driver(s3c24xx_uda134x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MODULE_DESCRIPTION("S3C24XX_UDA134X ALSA SoC audio driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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