^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * s3c24xx-i2s.c -- ALSA Soc Audio Layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2005 Wolfson Microelectronics PLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Graeme Gregory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Revision history
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 10th Nov 2006 Initial version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef S3C24XXI2S_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define S3C24XXI2S_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* clock sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S3C24XX_CLKSRC_PCLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define S3C24XX_CLKSRC_MPLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Clock dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S3C24XX_DIV_MCLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S3C24XX_DIV_BCLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define S3C24XX_DIV_PRESCALER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S3C24XX_PRESCALE(a,b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) (((a - 1) << S3C2410_IISPSR_INTSHIFT) | ((b - 1) << S3C2410_IISPSR_EXTSHFIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 s3c24xx_i2s_get_clockrate(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #endif /*S3C24XXI2S_H_*/