Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // s3c24xx-i2s.c  --  ALSA Soc Audio Layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // (c) 2006 Wolfson Microelectronics PLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) // Copyright 2004-2005 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) //	http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) //	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "regs-iis.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "s3c24xx-i2s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static struct snd_dmaengine_dai_dma_data s3c24xx_i2s_pcm_stereo_out = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	.chan_name	= "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	.addr_width	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static struct snd_dmaengine_dai_dma_data s3c24xx_i2s_pcm_stereo_in = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	.chan_name	= "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	.addr_width	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) struct s3c24xx_i2s_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	void __iomem	*regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct clk	*iis_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u32		iiscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u32		iismod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u32		iisfcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u32		iispsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static struct s3c24xx_i2s_info s3c24xx_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static void s3c24xx_snd_txctrl(int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u32 iisfcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u32 iiscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u32 iismod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	iiscon  = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	iismod  = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		iiscon  |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		iiscon  &= ~S3C2410_IISCON_TXIDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		iismod  |= S3C2410_IISMOD_TXMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		/* note, we have to disable the FIFOs otherwise bad things
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		 * seem to happen when the DMA stops. According to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		 * Samsung supplied kernel, this should allow the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		 * engine and FIFOs to reset. If this isn't allowed, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		 * DMA engine will simply freeze randomly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		iisfcon &= ~S3C2410_IISFCON_TXENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		iisfcon &= ~S3C2410_IISFCON_TXDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		iiscon  |=  S3C2410_IISCON_TXIDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		iiscon  &= ~S3C2410_IISCON_TXDMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		iismod  &= ~S3C2410_IISMOD_TXMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static void s3c24xx_snd_rxctrl(int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u32 iisfcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u32 iiscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	u32 iismod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	iiscon  = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	iismod  = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		iiscon  |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		iiscon  &= ~S3C2410_IISCON_RXIDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		iismod  |= S3C2410_IISMOD_RXMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		/* note, we have to disable the FIFOs otherwise bad things
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		 * seem to happen when the DMA stops. According to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		 * Samsung supplied kernel, this should allow the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		 * engine and FIFOs to reset. If this isn't allowed, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		 * DMA engine will simply freeze randomly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		iisfcon &= ~S3C2410_IISFCON_RXENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		iisfcon &= ~S3C2410_IISFCON_RXDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		iiscon  |= S3C2410_IISCON_RXIDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		iiscon  &= ~S3C2410_IISCON_RXDMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		iismod  &= ~S3C2410_IISMOD_RXMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * Wait for the LR signal to allow synchronisation to the L/R clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * from the codec. May only be needed for slave mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int s3c24xx_snd_lrsync(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	u32 iiscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	int timeout = 50; /* 5ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		if (iiscon & S3C2410_IISCON_LRINDEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		if (!timeout--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * Check whether CPU is the master or slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static inline int s3c24xx_snd_is_clkmaster(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  * Set S3C24xx I2S DAI format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int s3c24xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u32 iismod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	pr_debug("hw_params r: IISMOD: %x \n", iismod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		iismod |= S3C2410_IISMOD_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		iismod &= ~S3C2410_IISMOD_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		iismod |= S3C2410_IISMOD_MSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		iismod &= ~S3C2410_IISMOD_MSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	pr_debug("hw_params w: IISMOD: %x \n", iismod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 				 struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				 struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct snd_dmaengine_dai_dma_data *dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	u32 iismod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	dma_data = snd_soc_dai_get_dma_data(dai, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	/* Working copies of register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	pr_debug("hw_params r: IISMOD: %x\n", iismod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	switch (params_width(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		iismod &= ~S3C2410_IISMOD_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		dma_data->addr_width = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		iismod |= S3C2410_IISMOD_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		dma_data->addr_width = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	pr_debug("hw_params w: IISMOD: %x\n", iismod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			       struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		if (!s3c24xx_snd_is_clkmaster()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			ret = s3c24xx_snd_lrsync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 				goto exit_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			s3c24xx_snd_rxctrl(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			s3c24xx_snd_txctrl(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			s3c24xx_snd_rxctrl(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			s3c24xx_snd_txctrl(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) exit_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * Set S3C24xx Clock source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int s3c24xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	int clk_id, unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	iismod &= ~S3C2440_IISMOD_MPLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	switch (clk_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	case S3C24XX_CLKSRC_PCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	case S3C24XX_CLKSRC_MPLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		iismod |= S3C2440_IISMOD_MPLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)  * Set S3C24xx Clock dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int s3c24xx_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	int div_id, int div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	switch (div_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	case S3C24XX_DIV_BCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	case S3C24XX_DIV_MCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	case S3C24XX_DIV_PRESCALER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)  * To avoid duplicating clock code, allow machine driver to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)  * get the clockrate from here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 s3c24xx_i2s_get_clockrate(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	return clk_get_rate(s3c24xx_i2s.iis_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int s3c24xx_i2s_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	snd_soc_dai_init_dma_data(dai, &s3c24xx_i2s_pcm_stereo_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 					&s3c24xx_i2s_pcm_stereo_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	s3c24xx_i2s.iis_clk = devm_clk_get(dai->dev, "iis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	if (IS_ERR(s3c24xx_i2s.iis_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		pr_err("failed to get iis_clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		return PTR_ERR(s3c24xx_i2s.iis_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	ret = clk_prepare_enable(s3c24xx_i2s.iis_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	s3c24xx_snd_txctrl(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	s3c24xx_snd_rxctrl(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int s3c24xx_i2s_suspend(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	s3c24xx_i2s.iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	s3c24xx_i2s.iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	clk_disable_unprepare(s3c24xx_i2s.iis_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int s3c24xx_i2s_resume(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	ret = clk_prepare_enable(s3c24xx_i2s.iis_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define s3c24xx_i2s_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define s3c24xx_i2s_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define S3C24XX_I2S_RATES \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const struct snd_soc_dai_ops s3c24xx_i2s_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	.trigger	= s3c24xx_i2s_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	.hw_params	= s3c24xx_i2s_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	.set_fmt	= s3c24xx_i2s_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	.set_clkdiv	= s3c24xx_i2s_set_clkdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	.set_sysclk	= s3c24xx_i2s_set_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static struct snd_soc_dai_driver s3c24xx_i2s_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	.probe = s3c24xx_i2s_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	.playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		.channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		.channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		.rates = S3C24XX_I2S_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	.capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		.channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		.channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		.rates = S3C24XX_I2S_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	.ops = &s3c24xx_i2s_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static const struct snd_soc_component_driver s3c24xx_i2s_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	.name		= "s3c24xx-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	.suspend	= s3c24xx_i2s_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	.resume		= s3c24xx_i2s_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static int s3c24xx_iis_dev_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	s3c24xx_i2s.regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	if (IS_ERR(s3c24xx_i2s.regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		return PTR_ERR(s3c24xx_i2s.regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	s3c24xx_i2s_pcm_stereo_out.addr = res->start + S3C2410_IISFIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	s3c24xx_i2s_pcm_stereo_in.addr = res->start + S3C2410_IISFIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	ret = samsung_asoc_dma_platform_register(&pdev->dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 						 "tx", "rx", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		dev_err(&pdev->dev, "Failed to register the DMA: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 			&s3c24xx_i2s_component, &s3c24xx_i2s_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		dev_err(&pdev->dev, "Failed to register the DAI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static struct platform_driver s3c24xx_iis_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	.probe  = s3c24xx_iis_dev_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		.name = "s3c24xx-iis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) module_platform_driver(s3c24xx_iis_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Module information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MODULE_ALIAS("platform:s3c24xx-iis");