Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // ALSA Soc Audio Layer - S3C2412 I2S driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (c) 2006 Wolfson Microelectronics PLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) //	Graeme Gregory graeme.gregory@wolfsonmicro.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) //	linux@wolfsonmicro.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) // Copyright (c) 2007, 2004-2005 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) //	http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) //	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "regs-i2s-v2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "s3c2412-i2s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/platform_data/asoc-s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static struct snd_dmaengine_dai_dma_data s3c2412_i2s_pcm_stereo_out = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	.chan_name	= "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	.addr_width	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static struct snd_dmaengine_dai_dma_data s3c2412_i2s_pcm_stereo_in = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	.chan_name	= "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	.addr_width	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static struct s3c_i2sv2_info s3c2412_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static int s3c2412_i2s_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	pr_debug("Entered %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	snd_soc_dai_init_dma_data(dai, &s3c2412_i2s_pcm_stereo_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 					&s3c2412_i2s_pcm_stereo_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	ret = s3c_i2sv2_probe(dai, &s3c2412_i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	s3c2412_i2s.dma_capture = &s3c2412_i2s_pcm_stereo_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	s3c2412_i2s.dma_playback = &s3c2412_i2s_pcm_stereo_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	s3c2412_i2s.iis_cclk = devm_clk_get(dai->dev, "i2sclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	if (IS_ERR(s3c2412_i2s.iis_cclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		pr_err("failed to get i2sclk clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		ret = PTR_ERR(s3c2412_i2s.iis_cclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/* Set MPLL as the source for IIS CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	clk_set_parent(s3c2412_i2s.iis_cclk, clk_get(NULL, "mpll"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	ret = clk_prepare_enable(s3c2412_i2s.iis_cclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	s3c_i2sv2_cleanup(dai, &s3c2412_i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static int s3c2412_i2s_remove(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	clk_disable_unprepare(s3c2412_i2s.iis_cclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	s3c_i2sv2_cleanup(dai, &s3c2412_i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 				 struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 				 struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct s3c_i2sv2_info *i2s = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u32 iismod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	pr_debug("Entered %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	iismod = readl(i2s->regs + S3C2412_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	switch (params_width(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		iismod |= S3C2412_IISMOD_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		iismod &= ~S3C2412_IISMOD_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	writel(iismod, i2s->regs + S3C2412_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int s3c2412_i2s_suspend(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct s3c_i2sv2_info *i2s = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u32 iismod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (component->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		/* some basic suspend checks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		iismod = readl(i2s->regs + S3C2412_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			pr_warn("%s: RXDMA active?\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			pr_warn("%s: TXDMA active?\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		if (iismod & S3C2412_IISCON_IIS_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			pr_warn("%s: IIS active\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int s3c2412_i2s_resume(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct s3c_i2sv2_info *i2s = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	pr_info("component_active %d, IISMOD %08x, IISCON %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		component->active, i2s->suspend_iismod, i2s->suspend_iiscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (component->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		       i2s->regs + S3C2412_IISFIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		ndelay(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		writel(0x0, i2s->regs + S3C2412_IISFIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define s3c2412_i2s_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define s3c2412_i2s_resume  NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define S3C2412_I2S_RATES \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct snd_soc_dai_ops s3c2412_i2s_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.hw_params	= s3c2412_i2s_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct snd_soc_dai_driver s3c2412_i2s_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.probe		= s3c2412_i2s_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.remove	= s3c2412_i2s_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		.channels_min	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		.channels_max	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		.rates		= S3C2412_I2S_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		.formats	= SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		.channels_min	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		.channels_max	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		.rates		= S3C2412_I2S_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.formats	= SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.ops = &s3c2412_i2s_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct snd_soc_component_driver s3c2412_i2s_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.name		= "s3c2412-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.suspend	= s3c2412_i2s_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.resume		= s3c2412_i2s_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int s3c2412_iis_dev_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct s3c_audio_pdata *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		dev_err(&pdev->dev, "missing platform data");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	s3c2412_i2s.regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (IS_ERR(s3c2412_i2s.regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		return PTR_ERR(s3c2412_i2s.regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	s3c2412_i2s_pcm_stereo_out.addr = res->start + S3C2412_IISTXD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	s3c2412_i2s_pcm_stereo_out.filter_data = pdata->dma_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	s3c2412_i2s_pcm_stereo_in.addr = res->start + S3C2412_IISRXD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	s3c2412_i2s_pcm_stereo_in.filter_data = pdata->dma_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	ret = samsung_asoc_dma_platform_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 						 pdata->dma_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 						 "tx", "rx", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		pr_err("failed to register the DMA: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	ret = s3c_i2sv2_register_component(&pdev->dev, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 					   &s3c2412_i2s_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 					   &s3c2412_i2s_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		pr_err("failed to register the dai\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static struct platform_driver s3c2412_iis_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.probe  = s3c2412_iis_dev_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		.name = "s3c2412-iis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) module_platform_driver(s3c2412_iis_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Module information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MODULE_DESCRIPTION("S3C2412 I2S SoC Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MODULE_ALIAS("platform:s3c2412-iis");