^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA Soc Audio Layer - S3C_I2SV2 I2S driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2007 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* This code is the core support for the I2S block found in a number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Samsung SoC devices which is unofficially named I2S-V2. Currently the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * S3C2412 and the S3C64XX series use this block to provide 1 or 2 I2S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * channels via configurable GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef __SND_SOC_S3C24XX_S3C_I2SV2_I2S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define __SND_SOC_S3C24XX_S3C_I2SV2_I2S_H __FILE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S3C_I2SV2_DIV_BCLK (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define S3C_I2SV2_DIV_RCLK (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S3C_I2SV2_DIV_PRESCALER (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define S3C_I2SV2_CLKSRC_PCLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define S3C_I2SV2_CLKSRC_AUDIOBUS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define S3C_I2SV2_CLKSRC_CDCLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Set this flag for I2S controllers that have the bit IISMOD[12]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * bridge/break RCLK signal and external Xi2sCDCLK pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define S3C_FEATURE_CDCLKCON (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * struct s3c_i2sv2_info - S3C I2S-V2 information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @dev: The parent device passed to use from the probe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @regs: The pointer to the device registe block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @feature: Set of bit-flags indicating features of the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @master: True if the I2S core is the I2S bit clock master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * @dma_playback: DMA information for playback channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * @dma_capture: DMA information for capture channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * @suspend_iismod: PM save for the IISMOD register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @suspend_iiscon: PM save for the IISCON register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @suspend_iispsr: PM save for the IISPSR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * This is the private codec state for the hardware associated with an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * I2S channel such as the register mappings and clock sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct s3c_i2sv2_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct clk *iis_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct clk *iis_cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned char master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct snd_dmaengine_dai_dma_data *dma_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct snd_dmaengine_dai_dma_data *dma_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 suspend_iismod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 suspend_iiscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 suspend_iispsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) extern struct clk *s3c_i2sv2_get_clock(struct snd_soc_dai *cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct s3c_i2sv2_rate_calc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int clk_div; /* for prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int fs_div; /* for root frame clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) extern int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int *fstab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int rate, struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * s3c_i2sv2_probe - probe for i2s device helper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @dai: The ASoC DAI structure supplied to the original probe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @i2s: Our local i2s structure to fill in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @base: The base address for the registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) extern int s3c_i2sv2_probe(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct s3c_i2sv2_info *i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * s3c_i2sv2_cleanup - cleanup resources allocated in s3c_i2sv2_probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @dai: The ASoC DAI structure supplied to the original probe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @i2s: Our local i2s structure to fill in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) extern void s3c_i2sv2_cleanup(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct s3c_i2sv2_info *i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * s3c_i2sv2_register_component - register component and dai with soc core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @dev: DAI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @id: DAI ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @drv: The driver structure to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Fill in any missing fields and then register the given dai with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * soc core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) extern int s3c_i2sv2_register_component(struct device *dev, int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) const struct snd_soc_component_driver *cmp_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct snd_soc_dai_driver *dai_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif /* __SND_SOC_S3C24XX_S3C_I2SV2_I2S_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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