Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *		      http://www.simtec.co.uk/products/SWLINUX/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * S3C2410 IIS register definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __SAMSUNG_REGS_IIS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __SAMSUNG_REGS_IIS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define S3C2410_IISCON			(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define S3C2410_IISCON_LRINDEX		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define S3C2410_IISCON_TXFIFORDY	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define S3C2410_IISCON_RXFIFORDY	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S3C2410_IISCON_TXDMAEN		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define S3C2410_IISCON_RXDMAEN		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S3C2410_IISCON_TXIDLE		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define S3C2410_IISCON_RXIDLE		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S3C2410_IISCON_PSCEN		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S3C2410_IISCON_IISEN		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define S3C2410_IISMOD			(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S3C2440_IISMOD_MPLL		(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define S3C2410_IISMOD_SLAVE		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define S3C2410_IISMOD_NOXFER		(0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define S3C2410_IISMOD_RXMODE		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define S3C2410_IISMOD_TXMODE		(2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S3C2410_IISMOD_TXRXMODE		(3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S3C2410_IISMOD_LR_LLOW		(0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S3C2410_IISMOD_LR_RLOW		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define S3C2410_IISMOD_IIS		(0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define S3C2410_IISMOD_MSB		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define S3C2410_IISMOD_8BIT		(0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define S3C2410_IISMOD_16BIT		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S3C2410_IISMOD_BITMASK		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S3C2410_IISMOD_256FS		(0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define S3C2410_IISMOD_384FS		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S3C2410_IISMOD_16FS		(0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S3C2410_IISMOD_32FS		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S3C2410_IISMOD_48FS		(2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S3C2410_IISMOD_FS_MASK		(3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S3C2410_IISPSR			(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S3C2410_IISPSR_INTMASK		(31 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S3C2410_IISPSR_INTSHIFT		(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S3C2410_IISPSR_EXTMASK		(31 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define S3C2410_IISPSR_EXTSHFIT		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define S3C2410_IISFCON			(0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define S3C2410_IISFCON_TXDMA		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define S3C2410_IISFCON_RXDMA		(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define S3C2410_IISFCON_TXENABLE	(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define S3C2410_IISFCON_RXENABLE	(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define S3C2410_IISFCON_TXMASK		(0x3f << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define S3C2410_IISFCON_TXSHIFT		(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define S3C2410_IISFCON_RXMASK		(0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define S3C2410_IISFCON_RXSHIFT		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define S3C2410_IISFIFO			(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #endif /* __SAMSUNG_REGS_IIS_H__ */