^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2007 Simtec Electronics <linux@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * S3C2412 IIS register definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __ASM_ARCH_REGS_S3C2412_IIS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __ASM_ARCH_REGS_S3C2412_IIS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define S3C2412_IISCON (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define S3C2412_IISMOD (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define S3C2412_IISFIC (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define S3C2412_IISPSR (0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define S3C2412_IISTXD (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S3C2412_IISRXD (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S5PC1XX_IISFICS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define S5PC1XX_IISTXDS 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S5PC1XX_IISCON_SW_RST (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define S5PC1XX_IISCON_FRXOFSTATUS (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define S5PC1XX_IISCON_FRXORINTEN (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define S5PC1XX_IISCON_FTXSURSTAT (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S5PC1XX_IISCON_FTXSURINTEN (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define S5PC1XX_IISCON_TXSDMAPAUSE (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define S5PC1XX_IISCON_TXSDMACTIVE (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define S3C64XX_IISCON_FTXURSTATUS (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S3C64XX_IISCON_FTXURINTEN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S3C64XX_IISCON_TXFIFO2_EMPTY (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S3C64XX_IISCON_TXFIFO1_EMPTY (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define S3C64XX_IISCON_TXFIFO2_FULL (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define S3C64XX_IISCON_TXFIFO1_FULL (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define S3C2412_IISCON_LRINDEX (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S3C2412_IISCON_TXFIFO_EMPTY (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S3C2412_IISCON_RXFIFO_EMPTY (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define S3C2412_IISCON_TXFIFO_FULL (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S3C2412_IISCON_RXFIFO_FULL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S3C2412_IISCON_TXDMA_PAUSE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S3C2412_IISCON_RXDMA_PAUSE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S3C2412_IISCON_TXCH_PAUSE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S3C2412_IISCON_RXCH_PAUSE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S3C2412_IISCON_TXDMA_ACTIVE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S3C2412_IISCON_RXDMA_ACTIVE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S3C2412_IISCON_IIS_ACTIVE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S5PC1XX_IISMOD_OPCLK_CDCLK_OUT (0 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define S5PC1XX_IISMOD_OPCLK_CDCLK_IN (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define S5PC1XX_IISMOD_OPCLK_BCLK_OUT (2 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define S5PC1XX_IISMOD_OPCLK_PCLK (3 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define S5PC1XX_IISMOD_OPCLK_MASK (3 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define S5PC1XX_IISMOD_TXS_IDMA (1 << 28) /* Sec_TXFIFO use I-DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define S5PC1XX_IISMOD_BLCS_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define S5PC1XX_IISMOD_BLCS_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define S5PC1XX_IISMOD_BLCP_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define S5PC1XX_IISMOD_BLCP_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define S3C64XX_IISMOD_C2DD_HHALF (1 << 21) /* Discard Higher-half */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define S3C64XX_IISMOD_C2DD_LHALF (1 << 20) /* Discard Lower-half */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define S3C64XX_IISMOD_C1DD_HHALF (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define S3C64XX_IISMOD_C1DD_LHALF (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define S3C64XX_IISMOD_DC2_EN (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define S3C64XX_IISMOD_DC1_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define S3C64XX_IISMOD_BLC_16BIT (0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define S3C64XX_IISMOD_BLC_8BIT (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define S3C64XX_IISMOD_BLC_24BIT (2 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define S3C64XX_IISMOD_BLC_MASK (3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define S3C2412_IISMOD_IMS_SYSMUX (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define S3C2412_IISMOD_SLAVE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define S3C2412_IISMOD_MODE_TXONLY (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define S3C2412_IISMOD_MODE_RXONLY (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define S3C2412_IISMOD_MODE_TXRX (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define S3C2412_IISMOD_MODE_MASK (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define S3C2412_IISMOD_LR_LLOW (0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define S3C2412_IISMOD_LR_RLOW (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define S3C2412_IISMOD_SDF_IIS (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define S3C2412_IISMOD_SDF_MSB (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define S3C2412_IISMOD_SDF_LSB (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define S3C2412_IISMOD_SDF_MASK (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define S3C2412_IISMOD_RCLK_256FS (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define S3C2412_IISMOD_RCLK_512FS (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define S3C2412_IISMOD_RCLK_384FS (2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define S3C2412_IISMOD_RCLK_768FS (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define S3C2412_IISMOD_RCLK_MASK (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define S3C2412_IISMOD_BCLK_32FS (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define S3C2412_IISMOD_BCLK_48FS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define S3C2412_IISMOD_BCLK_16FS (2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define S3C2412_IISMOD_BCLK_24FS (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define S3C2412_IISMOD_BCLK_MASK (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define S3C2412_IISMOD_8BIT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define S3C64XX_IISMOD_CDCLKCON (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define S3C2412_IISPSR_PSREN (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define S3C64XX_IISFIC_TX2COUNT(x) (((x) >> 24) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define S3C64XX_IISFIC_TX1COUNT(x) (((x) >> 16) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define S3C2412_IISFIC_TXFLUSH (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define S3C2412_IISFIC_RXFLUSH (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define S3C2412_IISFIC_TXCOUNT(x) (((x) >> 8) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define S3C2412_IISFIC_RXCOUNT(x) (((x) >> 0) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define S5PC1XX_IISFICS_TXFLUSH (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define S5PC1XX_IISFICS_TXCOUNT(x) (((x) >> 8) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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