Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // ALSA SoC Audio Layer - S3C PCM-Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (c) 2009 Samsung Electronics Co. Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // Author: Jaswinder Singh <jassisinghbrar@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // based upon I2S drivers by Ben Dooks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/platform_data/asoc-s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /*Register Offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define S3C_PCM_CTL		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define S3C_PCM_CLKCTL		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define S3C_PCM_TXFIFO		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define S3C_PCM_RXFIFO		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define S3C_PCM_IRQCTL		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define S3C_PCM_IRQSTAT		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define S3C_PCM_FIFOSTAT	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define S3C_PCM_CLRINT		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* PCM_CTL Bit-Fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define S3C_PCM_CTL_TXDIPSTICK_MASK	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define S3C_PCM_CTL_TXDIPSTICK_SHIFT	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define S3C_PCM_CTL_RXDIPSTICK_MASK	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define S3C_PCM_CTL_RXDIPSTICK_SHIFT	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define S3C_PCM_CTL_TXDMA_EN		(0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define S3C_PCM_CTL_RXDMA_EN		(0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define S3C_PCM_CTL_TXMSB_AFTER_FSYNC	(0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define S3C_PCM_CTL_RXMSB_AFTER_FSYNC	(0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define S3C_PCM_CTL_TXFIFO_EN		(0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define S3C_PCM_CTL_RXFIFO_EN		(0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define S3C_PCM_CTL_ENABLE		(0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* PCM_CLKCTL Bit-Fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define S3C_PCM_CLKCTL_SERCLK_EN	(0x1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define S3C_PCM_CLKCTL_SERCLKSEL_PCLK	(0x1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define S3C_PCM_CLKCTL_SCLKDIV_MASK	0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define S3C_PCM_CLKCTL_SYNCDIV_MASK	0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define S3C_PCM_CLKCTL_SCLKDIV_SHIFT	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define S3C_PCM_CLKCTL_SYNCDIV_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* PCM_TXFIFO Bit-Fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define S3C_PCM_TXFIFO_DVALID	(0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define S3C_PCM_TXFIFO_DATA_MSK	(0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /* PCM_RXFIFO Bit-Fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define S3C_PCM_RXFIFO_DVALID	(0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define S3C_PCM_RXFIFO_DATA_MSK	(0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* PCM_IRQCTL Bit-Fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define S3C_PCM_IRQCTL_IRQEN		(0x1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define S3C_PCM_IRQCTL_WRDEN		(0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define S3C_PCM_IRQCTL_TXEMPTYEN	(0x1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define S3C_PCM_IRQCTL_TXALMSTEMPTYEN	(0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define S3C_PCM_IRQCTL_TXFULLEN		(0x1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define S3C_PCM_IRQCTL_TXALMSTFULLEN	(0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define S3C_PCM_IRQCTL_TXSTARVEN	(0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define S3C_PCM_IRQCTL_TXERROVRFLEN	(0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define S3C_PCM_IRQCTL_RXEMPTEN		(0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define S3C_PCM_IRQCTL_RXALMSTEMPTEN	(0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define S3C_PCM_IRQCTL_RXFULLEN		(0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define S3C_PCM_IRQCTL_RXALMSTFULLEN	(0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define S3C_PCM_IRQCTL_RXSTARVEN	(0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define S3C_PCM_IRQCTL_RXERROVRFLEN	(0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /* PCM_IRQSTAT Bit-Fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define S3C_PCM_IRQSTAT_IRQPND		(0x1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define S3C_PCM_IRQSTAT_WRD_XFER	(0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define S3C_PCM_IRQSTAT_TXEMPTY		(0x1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define S3C_PCM_IRQSTAT_TXALMSTEMPTY	(0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define S3C_PCM_IRQSTAT_TXFULL		(0x1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define S3C_PCM_IRQSTAT_TXALMSTFULL	(0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define S3C_PCM_IRQSTAT_TXSTARV		(0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define S3C_PCM_IRQSTAT_TXERROVRFL	(0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define S3C_PCM_IRQSTAT_RXEMPT		(0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define S3C_PCM_IRQSTAT_RXALMSTEMPT	(0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define S3C_PCM_IRQSTAT_RXFULL		(0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define S3C_PCM_IRQSTAT_RXALMSTFULL	(0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define S3C_PCM_IRQSTAT_RXSTARV		(0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define S3C_PCM_IRQSTAT_RXERROVRFL	(0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* PCM_FIFOSTAT Bit-Fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define S3C_PCM_FIFOSTAT_TXCNT_MSK		(0x3f << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define S3C_PCM_FIFOSTAT_TXFIFOEMPTY		(0x1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define S3C_PCM_FIFOSTAT_TXFIFOALMSTEMPTY	(0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define S3C_PCM_FIFOSTAT_TXFIFOFULL		(0x1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define S3C_PCM_FIFOSTAT_TXFIFOALMSTFULL	(0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define S3C_PCM_FIFOSTAT_RXCNT_MSK		(0x3f << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define S3C_PCM_FIFOSTAT_RXFIFOEMPTY		(0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define S3C_PCM_FIFOSTAT_RXFIFOALMSTEMPTY	(0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define S3C_PCM_FIFOSTAT_RXFIFOFULL		(0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define S3C_PCM_FIFOSTAT_RXFIFOALMSTFULL	(0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  * struct s3c_pcm_info - S3C PCM Controller information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  * @lock: Spin lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  * @dev: The parent device passed to use from the probe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  * @regs: The pointer to the device register block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  * @sclk_per_fs: number of sclk per frame sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  * @idleclk: Whether to keep PCMSCLK enabled even when idle (no active xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  * @pclk: the PCLK_PCM (pcm) clock pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  * @cclk: the SCLK_AUDIO (audio-bus) clock pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  * @dma_playback: DMA information for playback channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  * @dma_capture: DMA information for capture channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct s3c_pcm_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct device	*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	void __iomem	*regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	unsigned int sclk_per_fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/* Whether to keep PCMSCLK enabled even when idle(no active xfer) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	unsigned int idleclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct clk	*pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct clk	*cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	struct snd_dmaengine_dai_dma_data *dma_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct snd_dmaengine_dai_dma_data *dma_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct snd_dmaengine_dai_dma_data s3c_pcm_stereo_out[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.addr_width	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.addr_width	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct snd_dmaengine_dai_dma_data s3c_pcm_stereo_in[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		.addr_width	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		.addr_width	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct s3c_pcm_info s3c_pcm[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void s3c_pcm_snd_txctrl(struct s3c_pcm_info *pcm, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	void __iomem *regs = pcm->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	u32 ctl, clkctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	clkctl = readl(regs + S3C_PCM_CLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	ctl = readl(regs + S3C_PCM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	ctl &= ~(S3C_PCM_CTL_TXDIPSTICK_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			 << S3C_PCM_CTL_TXDIPSTICK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		ctl |= S3C_PCM_CTL_TXDMA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		ctl |= S3C_PCM_CTL_TXFIFO_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		ctl |= S3C_PCM_CTL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		ctl |= (0x4<<S3C_PCM_CTL_TXDIPSTICK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		ctl &= ~S3C_PCM_CTL_TXDMA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		ctl &= ~S3C_PCM_CTL_TXFIFO_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		if (!(ctl & S3C_PCM_CTL_RXFIFO_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			ctl &= ~S3C_PCM_CTL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			if (!pcm->idleclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	writel(clkctl, regs + S3C_PCM_CLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	writel(ctl, regs + S3C_PCM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static void s3c_pcm_snd_rxctrl(struct s3c_pcm_info *pcm, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	void __iomem *regs = pcm->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	u32 ctl, clkctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	ctl = readl(regs + S3C_PCM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	clkctl = readl(regs + S3C_PCM_CLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	ctl &= ~(S3C_PCM_CTL_RXDIPSTICK_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			 << S3C_PCM_CTL_RXDIPSTICK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		ctl |= S3C_PCM_CTL_RXDMA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		ctl |= S3C_PCM_CTL_RXFIFO_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		ctl |= S3C_PCM_CTL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		ctl |= (0x20<<S3C_PCM_CTL_RXDIPSTICK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		ctl &= ~S3C_PCM_CTL_RXDMA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		ctl &= ~S3C_PCM_CTL_RXFIFO_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		if (!(ctl & S3C_PCM_CTL_TXFIFO_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			ctl &= ~S3C_PCM_CTL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			if (!pcm->idleclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	writel(clkctl, regs + S3C_PCM_CLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	writel(ctl, regs + S3C_PCM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int s3c_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			       struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	dev_dbg(pcm->dev, "Entered %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		spin_lock_irqsave(&pcm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			s3c_pcm_snd_rxctrl(pcm, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			s3c_pcm_snd_txctrl(pcm, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		spin_unlock_irqrestore(&pcm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		spin_lock_irqsave(&pcm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			s3c_pcm_snd_rxctrl(pcm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			s3c_pcm_snd_txctrl(pcm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		spin_unlock_irqrestore(&pcm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int s3c_pcm_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 				 struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 				 struct snd_soc_dai *socdai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	void __iomem *regs = pcm->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	int sclk_div, sync_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	u32 clkctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	dev_dbg(pcm->dev, "Entered %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	/* Strictly check for sample size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	switch (params_width(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	spin_lock_irqsave(&pcm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	/* Get hold of the PCMSOURCE_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	clkctl = readl(regs + S3C_PCM_CLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (clkctl & S3C_PCM_CLKCTL_SERCLKSEL_PCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		clk = pcm->pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		clk = pcm->cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	/* Set the SCLK divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	sclk_div = clk_get_rate(clk) / pcm->sclk_per_fs /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 					params_rate(params) / 2 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	clkctl &= ~(S3C_PCM_CLKCTL_SCLKDIV_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			<< S3C_PCM_CLKCTL_SCLKDIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	clkctl |= ((sclk_div & S3C_PCM_CLKCTL_SCLKDIV_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			<< S3C_PCM_CLKCTL_SCLKDIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	/* Set the SYNC divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	sync_div = pcm->sclk_per_fs - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	clkctl &= ~(S3C_PCM_CLKCTL_SYNCDIV_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 				<< S3C_PCM_CLKCTL_SYNCDIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	clkctl |= ((sync_div & S3C_PCM_CLKCTL_SYNCDIV_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 				<< S3C_PCM_CLKCTL_SYNCDIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	writel(clkctl, regs + S3C_PCM_CLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	spin_unlock_irqrestore(&pcm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	dev_dbg(pcm->dev, "PCMSOURCE_CLK-%lu SCLK=%ufs SCLK_DIV=%d SYNC_DIV=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 				clk_get_rate(clk), pcm->sclk_per_fs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 				sclk_div, sync_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int s3c_pcm_set_fmt(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			       unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	void __iomem *regs = pcm->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	dev_dbg(pcm->dev, "Entered %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	spin_lock_irqsave(&pcm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	ctl = readl(regs + S3C_PCM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		/* Nothing to do, IB_NF by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		dev_err(pcm->dev, "Unsupported clock inversion!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		/* Nothing to do, Master by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		dev_err(pcm->dev, "Unsupported master/slave format!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	case SND_SOC_DAIFMT_CONT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		pcm->idleclk = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	case SND_SOC_DAIFMT_GATED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		pcm->idleclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		dev_err(pcm->dev, "Invalid Clock gating request!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		ctl |= S3C_PCM_CTL_TXMSB_AFTER_FSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		ctl |= S3C_PCM_CTL_RXMSB_AFTER_FSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	case SND_SOC_DAIFMT_DSP_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		ctl &= ~S3C_PCM_CTL_TXMSB_AFTER_FSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		ctl &= ~S3C_PCM_CTL_RXMSB_AFTER_FSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		dev_err(pcm->dev, "Unsupported data format!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	writel(ctl, regs + S3C_PCM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	spin_unlock_irqrestore(&pcm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int s3c_pcm_set_clkdiv(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 						int div_id, int div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	switch (div_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	case S3C_PCM_SCLK_PER_FS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		pcm->sclk_per_fs = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int s3c_pcm_set_sysclk(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 				  int clk_id, unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	void __iomem *regs = pcm->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	u32 clkctl = readl(regs + S3C_PCM_CLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	switch (clk_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	case S3C_PCM_CLKSRC_PCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		clkctl |= S3C_PCM_CLKCTL_SERCLKSEL_PCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	case S3C_PCM_CLKSRC_MUX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		clkctl &= ~S3C_PCM_CLKCTL_SERCLKSEL_PCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		if (clk_get_rate(pcm->cclk) != freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 			clk_set_rate(pcm->cclk, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	writel(clkctl, regs + S3C_PCM_CLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const struct snd_soc_dai_ops s3c_pcm_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	.set_sysclk	= s3c_pcm_set_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	.set_clkdiv	= s3c_pcm_set_clkdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	.trigger	= s3c_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	.hw_params	= s3c_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	.set_fmt	= s3c_pcm_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int s3c_pcm_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	snd_soc_dai_init_dma_data(dai, pcm->dma_playback, pcm->dma_capture);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define S3C_PCM_RATES  SNDRV_PCM_RATE_8000_96000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define S3C_PCM_DAI_DECLARE			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	.symmetric_rates = 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	.probe = s3c_pcm_dai_probe,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	.ops = &s3c_pcm_dai_ops,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	.playback = {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		.channels_min	= 2,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		.channels_max	= 2,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		.rates		= S3C_PCM_RATES,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		.formats	= SNDRV_PCM_FMTBIT_S16_LE,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	},							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	.capture = {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		.channels_min	= 2,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		.channels_max	= 2,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 		.rates		= S3C_PCM_RATES,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		.formats	= SNDRV_PCM_FMTBIT_S16_LE,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static struct snd_soc_dai_driver s3c_pcm_dai[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		.name	= "samsung-pcm.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		S3C_PCM_DAI_DECLARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		.name	= "samsung-pcm.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		S3C_PCM_DAI_DECLARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const struct snd_soc_component_driver s3c_pcm_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	.name		= "s3c-pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int s3c_pcm_dev_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	struct s3c_pcm_info *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	struct resource *mem_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	struct s3c_audio_pdata *pcm_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	dma_filter_fn filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	/* Check for valid device index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	if ((pdev->id < 0) || pdev->id >= ARRAY_SIZE(s3c_pcm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 		dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	pcm_pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	if (pcm_pdata && pcm_pdata->cfg_gpio && pcm_pdata->cfg_gpio(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 		dev_err(&pdev->dev, "Unable to configure gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	pcm = &s3c_pcm[pdev->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	pcm->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	spin_lock_init(&pcm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	/* Default is 128fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	pcm->sclk_per_fs = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	pcm->regs = devm_ioremap_resource(&pdev->dev, mem_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	if (IS_ERR(pcm->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		return PTR_ERR(pcm->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	pcm->cclk = devm_clk_get(&pdev->dev, "audio-bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	if (IS_ERR(pcm->cclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		dev_err(&pdev->dev, "failed to get audio-bus clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		return PTR_ERR(pcm->cclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	ret = clk_prepare_enable(pcm->cclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	/* record our pcm structure for later use in the callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	dev_set_drvdata(&pdev->dev, pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	pcm->pclk = devm_clk_get(&pdev->dev, "pcm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	if (IS_ERR(pcm->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 		dev_err(&pdev->dev, "failed to get pcm clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 		ret = PTR_ERR(pcm->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 		goto err_dis_cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	ret = clk_prepare_enable(pcm->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 		goto err_dis_cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	s3c_pcm_stereo_in[pdev->id].addr = mem_res->start + S3C_PCM_RXFIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	s3c_pcm_stereo_out[pdev->id].addr = mem_res->start + S3C_PCM_TXFIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	filter = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	if (pcm_pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 		s3c_pcm_stereo_in[pdev->id].filter_data = pcm_pdata->dma_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 		s3c_pcm_stereo_out[pdev->id].filter_data = pcm_pdata->dma_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 		filter = pcm_pdata->dma_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	pcm->dma_capture = &s3c_pcm_stereo_in[pdev->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	pcm->dma_playback = &s3c_pcm_stereo_out[pdev->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	ret = samsung_asoc_dma_platform_register(&pdev->dev, filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 						 NULL, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 		dev_err(&pdev->dev, "failed to get register DMA: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 		goto err_dis_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	ret = devm_snd_soc_register_component(&pdev->dev, &s3c_pcm_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 					 &s3c_pcm_dai[pdev->id], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 		dev_err(&pdev->dev, "failed to get register DAI: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 		goto err_dis_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) err_dis_pm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) err_dis_pclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	clk_disable_unprepare(pcm->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) err_dis_cclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	clk_disable_unprepare(pcm->cclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int s3c_pcm_dev_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	struct s3c_pcm_info *pcm = &s3c_pcm[pdev->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 	clk_disable_unprepare(pcm->cclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	clk_disable_unprepare(pcm->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static struct platform_driver s3c_pcm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	.probe  = s3c_pcm_dev_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	.remove = s3c_pcm_dev_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 		.name = "samsung-pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) module_platform_driver(s3c_pcm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Module information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MODULE_DESCRIPTION("S3C PCM Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MODULE_ALIAS("platform:samsung-pcm");