^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA SoC Audio Layer - Samsung I2S Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2010 Samsung Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Jaswinder Singh <jassisinghbrar@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __SND_SOC_SAMSUNG_I2S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __SND_SOC_SAMSUNG_I2S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SAMSUNG_I2S_DAI "samsung-i2s"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SAMSUNG_I2S_DAI_SEC "samsung-i2s-sec"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SAMSUNG_I2S_DIV_BCLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SAMSUNG_I2S_RCLKSRC_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SAMSUNG_I2S_RCLKSRC_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SAMSUNG_I2S_CDCLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Operation clock for IIS logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SAMSUNG_I2S_OPCLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SAMSUNG_I2S_OPCLK_CDCLK_OUT 0 /* CODEC clock out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SAMSUNG_I2S_OPCLK_CDCLK_IN 1 /* CODEC clock in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SAMSUNG_I2S_OPCLK_BCLK_OUT 2 /* Bit clock out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SAMSUNG_I2S_OPCLK_PCLK 3 /* Audio bus clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #endif /* __SND_SOC_SAMSUNG_I2S_H */