^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2011 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Samsung I2S driver's register header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __SND_SOC_SAMSUNG_I2S_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __SND_SOC_SAMSUNG_I2S_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define I2SCON 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define I2SMOD 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define I2SFIC 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define I2SPSR 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define I2STXD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define I2SRXD 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define I2SFICS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define I2STXDS 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define I2SAHB 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define I2SSTR0 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define I2SSIZE 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define I2STRNCNT 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define I2SLVL0ADDR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define I2SLVL1ADDR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define I2SLVL2ADDR 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define I2SLVL3ADDR 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define I2SSTR1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define I2SVER 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define I2SFIC1 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define I2STDM 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define I2SFSTA 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CON_RSTCLR (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CON_FRXOFSTATUS (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CON_FRXORINTEN (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CON_FTXSURSTAT (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CON_FTXSURINTEN (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CON_TXSDMA_PAUSE (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CON_TXSDMA_ACTIVE (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CON_FTXURSTATUS (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CON_FTXURINTEN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CON_TXFIFO2_EMPTY (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CON_TXFIFO1_EMPTY (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CON_TXFIFO2_FULL (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CON_TXFIFO1_FULL (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CON_LRINDEX (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CON_TXFIFO_EMPTY (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CON_RXFIFO_EMPTY (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CON_TXFIFO_FULL (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CON_RXFIFO_FULL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CON_TXDMA_PAUSE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CON_RXDMA_PAUSE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CON_TXCH_PAUSE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CON_RXCH_PAUSE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CON_TXDMA_ACTIVE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CON_RXDMA_ACTIVE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CON_ACTIVE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MOD_OPCLK_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MOD_OPCLK_CDCLK_OUT (0 << MOD_OPCLK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MOD_OPCLK_CDCLK_IN (1 << MOD_OPCLK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MOD_OPCLK_BCLK_OUT (2 << MOD_OPCLK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MOD_OPCLK_PCLK (3 << MOD_OPCLK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MOD_OPCLK_MASK (3 << MOD_OPCLK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MOD_TXS_IDMA (1 << 28) /* Sec_TXFIFO use I-DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MOD_BLCS_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MOD_BLCS_16BIT (0 << MOD_BLCS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MOD_BLCS_8BIT (1 << MOD_BLCS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MOD_BLCS_24BIT (2 << MOD_BLCS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MOD_BLCS_MASK (3 << MOD_BLCS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MOD_BLCP_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MOD_C2DD_HHALF (1 << 21) /* Discard Higher-half */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MOD_C2DD_LHALF (1 << 20) /* Discard Lower-half */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MOD_C1DD_HHALF (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MOD_C1DD_LHALF (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MOD_DC2_EN (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MOD_DC1_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MOD_BLC_16BIT (0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MOD_BLC_8BIT (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MOD_BLC_24BIT (2 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MOD_BLC_MASK (3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MOD_TXONLY (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MOD_RXONLY (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MOD_TXRX (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MOD_MASK (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MOD_LRP_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MOD_LR_LLOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MOD_LR_RLOW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MOD_SDF_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MOD_SDF_IIS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MOD_SDF_MSB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MOD_SDF_LSB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MOD_SDF_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MOD_RCLK_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MOD_RCLK_256FS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MOD_RCLK_512FS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MOD_RCLK_384FS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MOD_RCLK_768FS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MOD_RCLK_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MOD_BCLK_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MOD_BCLK_32FS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MOD_BCLK_48FS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MOD_BCLK_16FS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MOD_BCLK_24FS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MOD_BCLK_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MOD_8BIT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define EXYNOS5420_MOD_LRP_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define EXYNOS5420_MOD_SDF_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define EXYNOS5420_MOD_RCLK_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define EXYNOS5420_MOD_BCLK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define EXYNOS5420_MOD_BCLK_64FS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define EXYNOS5420_MOD_BCLK_96FS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define EXYNOS5420_MOD_BCLK_128FS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define EXYNOS5420_MOD_BCLK_192FS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define EXYNOS5420_MOD_BCLK_256FS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define EXYNOS5420_MOD_BCLK_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define EXYNOS7_MOD_RCLK_64FS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define EXYNOS7_MOD_RCLK_128FS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define EXYNOS7_MOD_RCLK_96FS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define EXYNOS7_MOD_RCLK_192FS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PSR_PSREN (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define FIC_TX2COUNT(x) (((x) >> 24) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define FIC_TX1COUNT(x) (((x) >> 16) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define FIC_TXFLUSH (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define FIC_RXFLUSH (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define FIC_TXCOUNT(x) (((x) >> 8) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define FIC_RXCOUNT(x) (((x) >> 0) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define FICS_TXCOUNT(x) (((x) >> 8) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AHB_INTENLVL0 (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AHB_LVL0INT (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AHB_CLRLVL0INT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AHB_DMARLD (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AHB_INTMASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AHB_DMAEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AHB_LVLINTMASK (0xf << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define I2SSIZE_TRNMSK (0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define I2SSIZE_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #endif /* __SND_SOC_SAMSUNG_I2S_REGS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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