^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Rockchip VAD driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _ROCKCHIP_VAD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _ROCKCHIP_VAD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define VAD_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define VAD_DET_CHNL_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define VAD_DET_CHNL_MASK GENMASK(31, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define VAD_DET_CHNL(x) ((x) << VAD_DET_CHNL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AUDIO_24BIT_SAT_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AUDIO_24BIT_SAT_MASK BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AUDIO_H16B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AUDIO_SAT_24TO16 BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AUDIO_24BIT_ALIGN_MODE_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AUDIO_24BIT_ALIGN_MODE_MASK BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AUDIO_24BIT_ALIGN_8_31B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AUDIO_24BIT_ALIGN_0_23B BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AUDIO_CHNL_BW_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AUDIO_CHNL_BW_MASK BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AUDIO_CHNL_16B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AUDIO_CHNL_24B BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AUDIO_CHNL_NUM_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AUDIO_CHNL_NUM_MASK GENMASK(25, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AUDIO_CHNL_NUM(x) ((x - 1) << AUDIO_CHNL_NUM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CFG_ACODE_AFTER_DET_EN_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CFG_ACODE_AFTER_DET_EN_MASK BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CFG_ACODE_AFTER_DET_EN BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define VAD_MODE_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define VAD_MODE_MASK GENMASK(21, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define STORE_DATA_VAD_DET_ONLY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define STORE_DATA_ALL (1 << VAD_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define NO_STORE_DATA (2 << VAD_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ACODE_CFG_REG_NUM_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ACODE_CFG_REG_NUM_MASK GENMASK(19, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ACODE_CFG_REG_NUM(x) ((x - 1) << ACODE_CFG_REG_NUM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SRC_ADDR_MODE_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SRC_ADDR_MODE_MASK BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SRC_ADDR_MODE_INC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SRC_ADDR_MODE_FIXED BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define INCR_BURST_LEN_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define INCR_BURST_LEN_MASK GENMASK(13, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define INCR_BURST_LEN(x) ((x - 1) << INCR_BURST_LEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SRC_BURST_NUM_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SRC_BURST_NUM_MASK GENMASK(9, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SRC_BURST_NUM(x) ((x - 1) << SRC_BURST_NUM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SRC_BURST_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SRC_BURST_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SRC_BURST_SIGNLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SRC_BURST_INCR (1 << SRC_BURST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SRC_BURST_INCR4 (3 << SRC_BURST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SRC_BURST_INCR8 (5 << SRC_BURST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SRC_BURST_INCR16 (7 << SRC_BURST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AUDIO_SRC_SEL_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AUDIO_SRC_SEL_MASK GENMASK(3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AUDIO_SRC_SEL_I2S0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AUDIO_SRC_SEL_I2S1 (1 << AUDIO_SRC_SEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AUDIO_SRC_SEL_I2S2 (2 << AUDIO_SRC_SEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AUDIO_SRC_SEL_I2S3 (3 << AUDIO_SRC_SEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AUDIO_SRC_SEL_PDM (4 << AUDIO_SRC_SEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define VAD_EN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VAD_EN_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VAD_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define VAD_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VAD_IS_ADDR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define VAD_ID_ADDR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define VAD_OD_ADDR0 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VAD_OD_ADDR1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define VAD_OD_ADDR2 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define VAD_OD_ADDR3 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define VAD_OD_ADDR4 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define VAD_OD_ADDR5 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define VAD_OD_ADDR6 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define VAD_OD_ADDR7 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define VAD_D_DATA0 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define VAD_D_DATA1 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define VAD_D_DATA2 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define VAD_D_DATA3 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define VAD_D_DATA4 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define VAD_D_DATA5 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define VAD_D_DATA6 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define VAD_D_DATA7 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define VAD_TIMEOUT 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define WORK_TIMEOUT_EN_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define WORK_TIMEOUT_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define WORK_TIMEOUT_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IDLE_TIMEOUT_EN_MASK BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IDLE_TIMEOUT_EN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IDLE_TIMEOUT_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define WORK_TIMEOUT_THD_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define WORK_TIMEOUT_THD_MASK GENMASK(29, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define WORK_TIMEOUT_THD(x) ((x) << WORK_TIMEOUT_THD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IDLE_TIMEOUT_THD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IDLE_TIMEOUT_THD_MASK GENMASK(19, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IDLE_TIMEOUT_THD(x) ((x) << IDLE_TIMEOUT_THD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define VAD_RAM_BEGIN_ADDR 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define VAD_RAM_END_ADDR 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define VAD_RAM_CUR_ADDR 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define VAD_DET_CON0 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define VAD_CON_THD_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VAD_CON_THD_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VAD_CON_THD(x) ((x) << VAD_CON_THD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define NOISE_LEVEL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define NOISE_LEVEL_MASK GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define NOISE_LEVEL(x) ((x) << NOISE_LEVEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GAIN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GAIN_MASK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GAIN(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define VAD_DET_CON1 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MIN_NOISE_FIND_MODE_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MIN_NOISE_FIN_MODE_MASK BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MIN_NOISE_FIND_MODE0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MIN_NOISE_FIND_MODE1 BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define NOISE_CLEAN_MODE_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define NOISE_CLEAN_MODE_MASK BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define NOISE_CLEAN_MODE0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define NOISE_CLEAN_MODE1 BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define NOISE_CLK_FORCE_EN_MASK BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define NOISE_CLK_AUTO_GATING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define NOISE_CLK_FORCE_EN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define NOISE_SAMPLE_NUM_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define NOISE_SAMPLE_NUM_MASK GENMASK(25, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define NOISE_SAMPLE_NUM ((x) << NOISE_SAMPLE_NUM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SOUND_THD_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SOUND_THD(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define VAD_DET_CON2 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IIR_B0_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IIR_B0_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IIR_B0(x) ((x) << IIR_B0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define NOISE_ALPHA_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define NOISE_ALPHA_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define NOISE_ALPHA(x) ((x) << NOISE_ALPHA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define NOISE_FRM_NUM_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define NOISE_FRM_NUM(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define VAD_DET_CON3 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IIR_B2_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IIR_B2(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IIR_B1_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IIR_B1(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define VAD_DET_CON4 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IIR_A2_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IIR_A2(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IIR_A1_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IIR_A1(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define VAD_DET_CON5 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IIR_RESULT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IIR_RESULT_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define NOISE_ABS_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define NOISE_ABS(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define VAD_INT 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define VAD_DATA_TRANS_INT_FLAG_MASK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define VAD_DATA_TRANS_INT_EN_MASK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define VAD_DATA_TRANS_INT_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define VAD_IDLE_MASK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define RAM_LOOP_FLGA_MASK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define WORK_TIMEOUT_FLAG_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IDLE_TIMEOUT_FLAG_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ERR_INT_FLAG_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define VAD_DET_INT_FLAG_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define WORK_TIMEOUT_INT_EN_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define WORK_TIMEOUT_INT_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IDLE_TIMEOUT_INT_EN_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IDLE_TIMEOUT_INT_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ERR_INT_EN_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ERR_INT_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define VAD_DET_INT_EN_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define VAD_DET_INT_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define VAD_AUX_CONTROL 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SAMPLE_CNT_EN_MASK BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SAMPLE_CNT_EN BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SAMPLE_CNT_DIS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define INT_TRIG_CTRL_EN_MASK BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define INT_TRIG_CTRL_EN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define INT_TRIG_CTRL_DIS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define INT_TRIG_VALID_THD_MASK GENMASK(27, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define INT_TRIG_VALID_THD(x) (((x) - 1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DATA_TRANS_KBYTE_THD_MASK GENMASK(11, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DATA_TRANS_KBYTE_THD(x) (((x) - 1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DATA_TRANS_TRIG_INT_EN_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DATA_TRANS_TRIG_INT_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DATA_TRANS_TRIG_INT_DIS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define RAM_ITF_EN_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define RAM_ITF_EN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define RAM_ITF_DIS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define BUS_WRITE_EN_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define BUS_WRITE_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define BUS_WRITE_DIS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define VAD_SAMPLE_CNT 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define VAD_NOISE_DATA 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* RK1808 SOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define RK1808_I2S0 0xff7e0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define RK1808_I2S1 0xff7f0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define RK1808_PDM 0xff800400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* RK3308 SOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define ACODEC_BASE 0xff560000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define ACODEC_ADC_ANA_CON0 0X340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define RK3308_I2S_8CH_0 0xff300800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define RK3308_I2S_8CH_1 0xff310800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define RK3308_I2S_8CH_2 0xff320800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define RK3308_I2S_8CH_3 0xff330800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define RK3308_PDM_8CH 0xff380400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* RK3568 SOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define RK3568_I2S_8CH_1 0xfe410800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define RK3568_I2S_2CH_2 0xfe420800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define RK3568_I2S_2CH_3 0xfe430800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define RK3568_PDM 0xfe440400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* RK3588 SOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define RK3588_I2S1_8CH 0xfe480800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define RK3588_PDM0 0xfe4b0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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