^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ALSA SoC Audio Layer - Rockchip SPDIF_RX Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _ROCKCHIP_SPDIFRX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _ROCKCHIP_SPDIFRX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* CFGR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SPDIFRX_CFGR_TWAD_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SPDIFRX_CFGR_TWAD_DATA_ONLY (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SPDIFRX_CFGR_TWAD_STREAM BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SPDIFRX_EN_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SPDIFRX_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SPDIFRX_DIS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* CLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SPDIFRX_CLR_RXSC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* CDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPDIFRX_CDR_CS_MASK GENMASK(10, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPDIFRX_CDR_AVGSEL_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPDIFRX_CDR_AVGSEL_MIN (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPDIFRX_CDR_AVGSEL_AVG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPDIFRX_CDR_BYPASS_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPDIFRX_CDR_BYPASS_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPDIFRX_CDR_BYPASS_DIS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* CDRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPDIFRX_CDRST_NOSTRTHR_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPDIFRX_CDRST_MAXCNT_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPDIFRX_CDRST_MINCNT_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* DMACR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPDIFRX_DMACR_RDE_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPDIFRX_DMACR_RDE_DISABLE (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPDIFRX_DMACR_RDE_ENABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPDIFRX_DMACR_RDL_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPDIFRX_DMACR_RDL(x) (((x) - 1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* FIFOCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPDIFRX_FIFOCTRL_RFL_MASK GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPDIFRX_FIFOCTRL_RFT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* INTEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPDIFRX_INTEN_UBCIE_MASK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPDIFRX_INTEN_UBCIE_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPDIFRX_INTEN_UBCIE_DIS (0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPDIFRX_INTEN_SYNCIE_MASK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPDIFRX_INTEN_SYNCIE_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPDIFRX_INTEN_SYNCIE_DIS (0 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPDIFRX_INTEN_BTEIE_MASK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPDIFRX_INTEN_BTEIE_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPDIFRX_INTEN_BTEIE_DIS (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPDIFRX_INTEN_NSYNCIE_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPDIFRX_INTEN_NSYNCIE_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPDIFRX_INTEN_NSYNCIE_DIS (0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* INTMASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SPDIFRX_INTMASK_UBCIMSK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPDIFRX_INTMASK_UBCIUMSK (0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPDIFRX_INTMASK_SYNCIMSK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SPDIFRX_INTMASK_SYNCIUMSK (0 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPDIFRX_INTMASK_BTEIMSK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SPDIFRX_INTMASK_BTEIUMSK (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SPDIFRX_INTMASK_NSYNCIMSK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SPDIFRX_INTMASK_NSYNCIUMSK (0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* INTSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SPDIFRX_INTSR_UBCISR_ACTIVE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SPDIFRX_INTSR_SYNCISR_ACTIVE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SPDIFRX_INTSR_BTEISR_ACTIVE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SPDIFRX_INTSR_NSYNCISR_ACTIVE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* INTCLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SPDIFRX_INTCLR_UBCICLR_MASK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SPDIFRX_INTCLR_UBCICLR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SPDIFRX_INTCLR_SYNCICLR_MASK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SPDIFRX_INTCLR_SYNCICLR BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SPDIFRX_INTCLR_BTECLR_MASK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SPDIFRX_INTCLR_BIECLR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SPDIFRX_INTCLR_NSYNCICLR_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SPDIFRX_INTCLR_NSYNCICLR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* BURSTINFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SPDIFRX_BURSTINFO_PD_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SPDIFRX_BURSTINFO_BSNUM_MASK GENMASK(15, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SPDIFRX_BURSTINFO_DATAINFO_MASK GENMASK(12, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SPDIFRX_BURSTINFO_ERRFLAG_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SPDIFRX_BURSTINFO_ERR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SPDIFRX_BURSTINFO_VALID (0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SPDIFRX_BURSTINFO_DATATYPE_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SPDIFRX_VERSION (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SPDIFRX_CFGR (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SPDIFRX_CLR (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SPDIFRX_CDR (0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SPDIFRX_CDRST (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SPDIFRX_DMACR (0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SPDIFRX_FIFOCTRL (0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SPDIFRX_INTEN (0x001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SPDIFRX_INTMASK (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SPDIFRX_INTSR (0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SPDIFRX_INTCLR (0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SPDIFRX_SMPDR (0x002C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SPDIFRX_USRDRN (0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SPDIFRX_CHNSRN (0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SPDIFRX_BURSTINFO (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #endif /* _ROCKCHIP_SPDIFRX_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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