Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * ALSA SoC Audio Layer - Rockchip SPDIF_RX Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "rockchip_spdifrx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) struct rk_spdifrx_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	struct clk *mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	struct clk *hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct snd_dmaengine_dai_dma_data capture_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct reset_control *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static int rk_spdifrx_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct rk_spdifrx_dev *spdifrx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	clk_disable_unprepare(spdifrx->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	clk_disable_unprepare(spdifrx->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static int rk_spdifrx_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct rk_spdifrx_dev *spdifrx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	ret = clk_prepare_enable(spdifrx->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		dev_err(spdifrx->dev, "mclk clock enable failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	ret = clk_prepare_enable(spdifrx->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		dev_err(spdifrx->dev, "hclk clock enable failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static int rk_spdifrx_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 				struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 				struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct rk_spdifrx_dev *spdifrx = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	regmap_update_bits(spdifrx->regmap, SPDIFRX_INTEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			   SPDIFRX_INTEN_SYNCIE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			   SPDIFRX_INTEN_NSYNCIE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			   SPDIFRX_INTEN_SYNCIE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			   SPDIFRX_INTEN_NSYNCIE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	regmap_update_bits(spdifrx->regmap, SPDIFRX_DMACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			   SPDIFRX_DMACR_RDL_MASK, SPDIFRX_DMACR_RDL(8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	regmap_update_bits(spdifrx->regmap, SPDIFRX_CDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			   SPDIFRX_CDR_AVGSEL_MASK | SPDIFRX_CDR_BYPASS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			   SPDIFRX_CDR_AVGSEL_MIN | SPDIFRX_CDR_BYPASS_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static void rk_spdifrx_reset(struct rk_spdifrx_dev *spdifrx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	reset_control_assert(spdifrx->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	reset_control_deassert(spdifrx->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static int rk_spdifrx_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			      int cmd, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct rk_spdifrx_dev *spdifrx = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		rk_spdifrx_reset(spdifrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		ret = regmap_update_bits(spdifrx->regmap, SPDIFRX_DMACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 					 SPDIFRX_DMACR_RDE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 					 SPDIFRX_DMACR_RDE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		ret = regmap_update_bits(spdifrx->regmap, SPDIFRX_CFGR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 					 SPDIFRX_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 					 SPDIFRX_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		ret = regmap_update_bits(spdifrx->regmap, SPDIFRX_DMACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 					 SPDIFRX_DMACR_RDE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 					 SPDIFRX_DMACR_RDE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		ret = regmap_update_bits(spdifrx->regmap, SPDIFRX_CFGR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 					 SPDIFRX_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 					 SPDIFRX_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int rk_spdifrx_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct rk_spdifrx_dev *spdifrx = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	dai->capture_dma_data = &spdifrx->capture_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct snd_soc_dai_ops rk_spdifrx_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.hw_params = rk_spdifrx_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.trigger = rk_spdifrx_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static struct snd_soc_dai_driver rk_spdifrx_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.probe = rk_spdifrx_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		.stream_name = "Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		.channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		.channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		.rates = (SNDRV_PCM_RATE_32000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			  SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			  SNDRV_PCM_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			  SNDRV_PCM_RATE_96000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			  SNDRV_PCM_RATE_192000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		.formats = (SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			    SNDRV_PCM_FMTBIT_S20_3LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			    SNDRV_PCM_FMTBIT_S24_LE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.ops = &rk_spdifrx_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct snd_soc_component_driver rk_spdifrx_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.name = "rockchip-spdifrx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static bool rk_spdifrx_wr_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	case SPDIFRX_CFGR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	case SPDIFRX_CLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	case SPDIFRX_CDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	case SPDIFRX_CDRST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	case SPDIFRX_DMACR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	case SPDIFRX_FIFOCTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	case SPDIFRX_INTEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	case SPDIFRX_INTMASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	case SPDIFRX_INTSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	case SPDIFRX_INTCLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	case SPDIFRX_SMPDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	case SPDIFRX_BURSTINFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static bool rk_spdifrx_rd_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	case SPDIFRX_CFGR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	case SPDIFRX_CLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	case SPDIFRX_CDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	case SPDIFRX_CDRST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	case SPDIFRX_DMACR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	case SPDIFRX_FIFOCTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	case SPDIFRX_INTEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	case SPDIFRX_INTMASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	case SPDIFRX_INTSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	case SPDIFRX_INTCLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	case SPDIFRX_SMPDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	case SPDIFRX_BURSTINFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static bool rk_spdifrx_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	case SPDIFRX_CLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	case SPDIFRX_CDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	case SPDIFRX_CDRST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	case SPDIFRX_FIFOCTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	case SPDIFRX_INTSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	case SPDIFRX_INTCLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	case SPDIFRX_SMPDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	case SPDIFRX_BURSTINFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static bool rk_spdifrx_precious_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	case SPDIFRX_SMPDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const struct regmap_config rk_spdifrx_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.max_register = SPDIFRX_BURSTINFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.writeable_reg = rk_spdifrx_wr_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.readable_reg = rk_spdifrx_rd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.volatile_reg = rk_spdifrx_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.precious_reg = rk_spdifrx_precious_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static irqreturn_t rk_spdifrx_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	struct rk_spdifrx_dev *spdifrx = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	u32 intsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	regmap_read(spdifrx->regmap, SPDIFRX_INTSR, &intsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (intsr & BIT(7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		dev_dbg(spdifrx->dev, "NSYNC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		regmap_write(spdifrx->regmap, SPDIFRX_INTCLR, BIT(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (intsr & BIT(9)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		dev_dbg(spdifrx->dev, "SYNC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		regmap_write(spdifrx->regmap, SPDIFRX_INTCLR, BIT(9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int rk_spdifrx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	struct rk_spdifrx_dev *spdifrx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (!spdifrx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	spdifrx->reset = devm_reset_control_get(&pdev->dev, "spdifrx-m");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (IS_ERR(spdifrx->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		ret = PTR_ERR(spdifrx->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		if (ret != -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	spdifrx->hclk = devm_clk_get(&pdev->dev, "hclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (IS_ERR(spdifrx->hclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		return PTR_ERR(spdifrx->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	spdifrx->mclk = devm_clk_get(&pdev->dev, "mclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	if (IS_ERR(spdifrx->mclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		return PTR_ERR(spdifrx->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	spdifrx->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (spdifrx->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return spdifrx->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	ret = devm_request_threaded_irq(&pdev->dev, spdifrx->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 					rk_spdifrx_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 					dev_name(&pdev->dev), spdifrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	spdifrx->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 						&rk_spdifrx_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	if (IS_ERR(spdifrx->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		return PTR_ERR(spdifrx->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	spdifrx->capture_dma_data.addr = res->start + SPDIFRX_SMPDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	spdifrx->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	spdifrx->capture_dma_data.maxburst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	spdifrx->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	dev_set_drvdata(&pdev->dev, spdifrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (!pm_runtime_enabled(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		ret = rk_spdifrx_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			goto err_pm_runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 					      &rk_spdifrx_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 					      &rk_spdifrx_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		dev_err(&pdev->dev, "Could not register DAI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		goto err_pm_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		dev_err(&pdev->dev, "Could not register PCM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		goto err_pm_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) err_pm_suspend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		rk_spdifrx_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) err_pm_runtime:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int rk_spdifrx_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		rk_spdifrx_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int rockchip_spdifrx_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	struct rk_spdifrx_dev *spdifrx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	regcache_mark_dirty(spdifrx->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int rockchip_spdifrx_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	struct rk_spdifrx_dev *spdifrx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	ret = regcache_sync(spdifrx->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const struct dev_pm_ops rk_spdifrx_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	SET_RUNTIME_PM_OPS(rk_spdifrx_runtime_suspend, rk_spdifrx_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 			   NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	SET_SYSTEM_SLEEP_PM_OPS(rockchip_spdifrx_suspend, rockchip_spdifrx_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const struct of_device_id rk_spdifrx_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	{ .compatible = "rockchip,rk3308-spdifrx", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MODULE_DEVICE_TABLE(of, rk_spdifrx_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static struct platform_driver rk_spdifrx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	.probe = rk_spdifrx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	.remove = rk_spdifrx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		.name = "rockchip-spdifrx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		.of_match_table = of_match_ptr(rk_spdifrx_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		.pm = &rk_spdifrx_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) module_platform_driver(rk_spdifrx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MODULE_ALIAS("platform:rockchip-spdifrx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MODULE_DESCRIPTION("ROCKCHIP SPDIFRX Controller Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MODULE_LICENSE("GPL v2");