Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * ALSA SoC Audio Layer - Rockchip SPDIF transceiver driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2015 Collabora Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef _ROCKCHIP_SPDIF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _ROCKCHIP_SPDIF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * CFGR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * transfer configuration register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SPDIF_CFGR_CLK_DIV_SHIFT	(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SPDIF_CFGR_CLK_DIV_MASK		(0xff << SPDIF_CFGR_CLK_DIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SPDIF_CFGR_CLK_DIV(x)		((x - 1) << SPDIF_CFGR_CLK_DIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SPDIF_CFGR_CSE_MASK		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SPDIF_CFGR_CSE_EN		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPDIF_CFGR_CSE_DIS		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPDIF_CFGR_ADJ_MASK		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPDIF_CFGR_ADJ_LEFT_J		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPDIF_CFGR_ADJ_RIGHT_J		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPDIF_CFGR_HALFWORD_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPDIF_CFGR_HALFWORD_DISABLE	(0 << SPDIF_CFGR_HALFWORD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPDIF_CFGR_HALFWORD_ENABLE	(1 << SPDIF_CFGR_HALFWORD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPDIF_CFGR_VDW_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPDIF_CFGR_VDW(x)	(x << SPDIF_CFGR_VDW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SDPIF_CFGR_VDW_MASK	(0xf << SPDIF_CFGR_VDW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPDIF_CFGR_VDW_16	SPDIF_CFGR_VDW(0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPDIF_CFGR_VDW_20	SPDIF_CFGR_VDW(0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPDIF_CFGR_VDW_24	SPDIF_CFGR_VDW(0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  * DMACR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  * DMA control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPDIF_DMACR_TDE_SHIFT	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPDIF_DMACR_TDE_DISABLE	(0 << SPDIF_DMACR_TDE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPDIF_DMACR_TDE_ENABLE	(1 << SPDIF_DMACR_TDE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPDIF_DMACR_TDL_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPDIF_DMACR_TDL(x)	((x) << SPDIF_DMACR_TDL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPDIF_DMACR_TDL_MASK	(0x1f << SPDIF_DMACR_TDL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)  * XFER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)  * Transfer control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPDIF_XFER_TXS_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPDIF_XFER_TXS_STOP	(0 << SPDIF_XFER_TXS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPDIF_XFER_TXS_START	(1 << SPDIF_XFER_TXS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPDIF_CFGR	(0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SPDIF_SDBLR	(0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPDIF_DMACR	(0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SPDIF_INTCR	(0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPDIF_INTSR	(0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPDIF_XFER	(0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SPDIF_SMPDR	(0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPDIF_VLDFRn(x)	(0x0060 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SPDIF_USRDRn(x)	(0x0090 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SPDIF_CHNSRn(x)	(0x00c0 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SPDIF_VERSION	(0x01c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif /* _ROCKCHIP_SPDIF_H */