^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Rockchip PDM ALSA SoC Digital Audio Interface(DAI) driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _ROCKCHIP_PDM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _ROCKCHIP_PDM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* PDM REGS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PDM_SYSCONFIG (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PDM_CTRL0 (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PDM_CTRL1 (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PDM_CLK_CTRL (0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PDM_HPF_CTRL (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PDM_FIFO_CTRL (0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PDM_DMA_CTRL (0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PDM_INT_EN (0x001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PDM_INT_CLR (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PDM_INT_ST (0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PDM_RXFIFO_DATA (0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PDM_DATA_VALID (0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PDM_VERSION (0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* PDM_SYSCONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PDM_RX_MASK (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PDM_RX_START (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PDM_RX_STOP (0x0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PDM_RX_CLR_MASK (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PDM_RX_CLR_WR (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PDM_RX_CLR_DONE (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* PDM CTRL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PDM_PATH_MSK (0xf << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PDM_MODE_MSK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PDM_MODE_RJ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PDM_MODE_LJ BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PDM_PATH3_EN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PDM_PATH2_EN BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PDM_PATH1_EN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PDM_PATH0_EN BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PDM_HWT_EN BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PDM_SAMPLERATE_MSK GENMASK(7, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PDM_SAMPLERATE(x) ((x) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PDM_VDW_MSK (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PDM_VDW(X) ((X - 1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* PDM CTRL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PDM_FD_NUMERATOR_SFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PDM_FD_NUMERATOR_MSK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PDM_FD_DENOMINATOR_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PDM_FD_DENOMINATOR_MSK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* PDM CLK CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PDM_PATH_SHIFT(x) (8 + (x) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PDM_PATH_MASK(x) (0x3 << PDM_PATH_SHIFT(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PDM_PATH(x, v) ((v) << PDM_PATH_SHIFT(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PDM_CLK_FD_RATIO_MSK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PDM_CLK_FD_RATIO_40 (0X0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PDM_CLK_FD_RATIO_35 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PDM_CLK_MSK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PDM_CLK_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PDM_CLK_DIS (0x0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PDM_CKP_MSK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PDM_CKP_NORMAL (0x0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PDM_CKP_INVERTED BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PDM_DS_RATIO_MSK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PDM_CLK_320FS (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PDM_CLK_640FS (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PDM_CLK_1280FS (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PDM_CLK_2560FS (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PDM_CLK_5120FS (0x4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PDM_CIC_RATIO_MSK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* PDM HPF CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PDM_HPF_LE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PDM_HPF_RE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PDM_HPF_CF_MSK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PDM_HPF_3P79HZ (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PDM_HPF_60HZ (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PDM_HPF_243HZ (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PDM_HPF_493HZ (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* PDM FIFO CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PDM_FIFO_CNT(x) ((x) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* PDM DMA CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PDM_DMA_RD_MSK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PDM_DMA_RD_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PDM_DMA_RD_DIS (0x0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PDM_DMA_RDL_MSK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PDM_DMA_RDL(X) ((X - 1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #endif /* _ROCKCHIP_PDM_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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